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CY7C1306V25 Datasheet

  • CY7C1306V25

  • Memory

  • 28頁

  • ETC

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Preliminary
CY7C1303V25
CY7C1306V25
18 Mb Burst of 2 Pipelined SRAM with QDR Architecture
Features
鈥?Separate Independent Read and Write Data Ports
鈥?Supports concurrent transactions
鈥?167 MHz Clock for High Bandwidth
鈥?2.5 ns Clock-to-Valid access time
鈥?2-Word Burst on all accesses
鈥?Double Data Rate (DDR) interfaces on both Read & Write
Ports (data transferred at 333 MHz) @167 MHz
鈥?Two input clocks (K and K) for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) accounts for clock skew
and flight time mis-matches
鈥?Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
鈥?Separate Port Selects for depth expansion
鈥?Synchronous internally self-timed writes
鈥?2.5V core power supply with HSTL Inputs and Outputs
鈥?13x15 mm 1.0 mm pitch fBGA package, 165 ball
(11x15 matrix) Variable drive HSTL output buffers
鈥?Expanded HSTL output voltage (1.4V鈥?.9V)
鈥?JTAG Interface
鈥?Variable Impedance HSTL
Functional Description
The CY7C1303V25 and CY7C1306V25 are 2.5V Synchro-
nous Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the mem-
ory array. The Read port has dedicated Data Outputs to sup-
port Read operations and the Write Port has dedicated Data
inputs to support Write operations. Access to each port is ac-
complished through a common address bus. The Read ad-
dress is latched on the rising edge of the K clock and the Write
address is latched on the rising edge of K clock. QDR has
separate data inputs and data outputs to completely eliminate
the need to 鈥渢urn-around鈥?the data bus required with common
I/O devices. Accesses to the CY7C1303V25/CY7C1306V25
Read and Write ports are completely independent of one an-
other. All accesses are initiated synchronously on the rising
edge of the positive input clock (K). In order to maximize data
throughput, both Read and Write ports are equipped with Dou-
ble Data Rate (DDR) interfaces. Therefore, data can be trans-
ferred into the device on every rising edge of both input clocks
(K and K) and out of the device on every rising edge of the
output clock (C and C) thereby maximizing performance while
simplifying system design. Each address location is associat-
ed with two 18-bit words (CY7C1303V25) or two 36-bit words
(CY7C1306V25) that burst sequentially into or out of the de-
vice.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate inde-
pendently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1303V25 鈥?1 Mb x 18
CY7C1306V25 鈥?512K x 36
Logic Block Diagram (CY7C1303V25)
D
[17:0]
18
Write
Data Reg
Write Add. Decode
Write
Data Reg
Read Add. Decode
A
(18:0)
19
Address
Register
Address
Register
19
A
(18:0)
K
K
512Kx18
Memory
Array
512Kx18
Memory
Array
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
36
Vref
WPS
BWS
0
BWS
1
Control
Logic
18
Reg.
18
Reg.
18
Reg. 18
18
Q
[17:0]
Cypress Semiconductor Corporation
Document #: 38-05100 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 11, 2002

CY7C1306V25相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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