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CY7C1302V25 Datasheet

  • CY7C1302V25

  • Memory

  • 19頁

  • ETC

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CY7C1302V25
9-Mb Pipelined SRAM with QDR鈩?Architecture
Features
鈥?Separate independent read and write data ports
鈥?Supports concurrent transactions
鈥?167-MHz clock for high bandwidth
鈥?2.5-ns clock-to-valid access time
鈥?Two-word burst on all accesses
鈥?Double data rate (DDR) interfaces on both read and
write ports (data transferred at 333 MHz) @ 167 MHz
鈥?Two input clocks (K and K)
[1]
for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) account for clock skew
and flight time mismatches
鈥?Single multiplexed address input bus latches address
inputs for both read and write ports
鈥?Separate port selects for depth expansion
鈥?Synchronous internally self-timed writes
鈥?2.5V core power supply with HSTL inputs and outputs
[1]
鈥?13 脳 15 mm 鈥?1.0-mm pitch FBGA package, 165 ball
(11 脳 15 matrix)
鈥?Variable-drive HSTL output buffers
鈥?Expanded HSTL output voltage (1.4V鈥?.9V)
鈥?JTAG interface
鈥?Variable impedance HSTL
Functional Description
The CY7C1302V25 is a 2.5V synchronous pipelined SRAM
with QDR鈩?architecture. QDR architecture consists of two
separate ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data inputs to support Write opera-
tions. Access to each port is accomplished through a common
address bus. The Read address is latched on the rising edge
of the K
[1]
clock and the Write address is latched on the rising
edge of K
[1]
clock. QDR has separate data inputs and data
outputs to completely eliminate the need to 鈥渢urn-around鈥?the
data bus required with common I/O devices. Accesses to the
CY7C1302V25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K)
[1]
. In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K)
[1]
and out of the device on every rising
edge of the output clock (C and C) thereby maximizing perfor-
mance while simplifying system design.
Depth expansion is accomplished with Port Select inputs for
each port. This allows the ports to operate independently.
All synchronous inputs pass through input registers controlled
by the input clocks (K and K)
[1]
. All data outputs pass through
output registers controlled by the output clocks (C or C). Writes
occur with on-chip synchronous self-timed write circuitry.
Logic Block Diagram
D
[17:0]
18
Write
Data Reg
Write Add. Decode
Write
Data Reg
Read Add. Decode
A
l17:0]
18
K
[1]
K
[1]
Address
Register
Address
Register
18
A
[17:0]
256Kx18
Memory
Array
256Kx18
Memory
Array
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
36
Vref
WPS
BWS
0
BWS
1
Control
Logic
18
Reg.
18
Reg.
18
Reg. 18
18
Q
[17:0]
Note:
1. K and K inputs require V
IH
to be greater than V
REF
+ 0.5V and V
IL
to be less than V
REF
鈥?0.5V. This is a subset of JEDEC standards for HSTL I/Os.
Cypress Semiconductor Corporation
Document #: 38-05260 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 12, 2002

CY7C1302V25相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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