鈥?/div>
Fast Clock Speed: 100 and 83 MHz
Fast Access Times: 5.0/6.0 ns Max.
Single Clock Operation
Single 3.3V 鈥?% and +5% power supply VCC
Separate V
CCQ
for output buffer
Two Chip Enables for simple depth expansion
Address, Data Input, CE1X, CE2X, CE1Y, CE2Y, PTX,
PTY, WEX, WEY, and Data Output Registers On-Chip
Concurrent Reads and Writes
Two bidirectional Data Buses
Can be configured as separate I/O
Pass-Through feature
Asynchronous Output Enables (OEX, OEY)
LVTTL-Compatible I/O
Self-Timed write
Automatic power-down
176-Pin TQFP Package
The CY7C1301A allows the user to concurrently perform
reads, writes, or pass-through cycles in combination on the
two data ports. The two address ports (AX, AY) determine the
read or write locations for their respective data ports (DQX,
DQY).
All input pins except Output Enable pins (OEX, OEY) are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, depth-expansion Chip Enables
(CE1X, CE2X, CE1Y and CE2Y), Pass-Through controls (PTX
and PTY), and Read-Write control (WEX and WEY).
The pass-through feature allows data to be passed from one
port to the other, in either direction. The PTX input must be
asserted to pass data from port X to port Y. The PTY will
likewise pass data from port Y to port X. A pass-through
operation takes precedence over a read operation.
For the case when AX and AY are the same, certain protocols
are followed. If both ports are read, the reads occur normally.
If one port is written and the other is read, the read from the
array will occur before the data is written. If both ports are
written, only the data on DQY will be written to the array.
The CY7C1301A operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible. These dual I/O,
dual address synchronous SRAMs are well suited for ATM,
Ethernet switches, routers, cell/frame buffers, SNA switches
and shared memory applications.
The CY7C1301A device needs one extra cycle after power for
proper power on reset. The extra cycle is needed after V
CC
is
stable on the device. This device is available in a 176-pin
TQFP package.
Functional Description
The CY7C1301A SRAM integrates 262,144 x 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
Logic Block Diagram
[1]
18/17
18/17
*AX
Address
Register
256K/128K x 9 x 4
SRAM Array
Address
Register
AY*
WEX#
Write X
Register
Write
Driver
Sensing
Amplifiers
Sensing
Amplifiers
Write
Driver
Write Y
Register
WEY#
PTX#
PTX
Register
Pass-Through
PTX
Register
PTY#
CLK
Data In
Register
Output
Register
Output
Register
Data In
Register
CLK
CE1X#
CE2X
Chip Enable
Register
Chip Enable
Register
DQX
DQY
Chip Enable
Register
Chip Enable
Register
CE1Y#
CE2Y
OEX#
OEY#
Note:
1. For 256 脳 36 device, AX and AY are 18-bit-wide buses.
Cypress Semiconductor Corporation
Document # 38-05076 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised January 19, 2003
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