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CY7C109D Datasheet

  • CY7C109D

  • 1-Mbit (128K x 8) Static RAM

  • 11頁

  • CYPRESS

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CY7C109D
CY7C1009D
1-Mbit (128K x 8) Static RAM
Features
鈥?Pin- and function-compatible with CY7C109B/CY7C1009B
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?I
CC
= 80 mA @ 10 ns
鈥?Low CMOS standby power
鈥?I
SB2
= 3 mA
鈥?2.0V Data Retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
, CE
2
and OE options
鈥?CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available
in Pb-free 32-pin 300-Mil wide Molded SOJ package
Functional Description
[1]
The CY7C109D/CY7C1009D is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW
Output Enable (OE), and tri-state drivers.The eight input and
output pins (IO
0
through IO
7
) are placed in a high-impedance
state when:
鈥?Deselected (CE
1
HIGH or CE
2
LOW),
鈥?Outputs are disabled (OE HIGH),
鈥?When the write operation is active (CE
1
LOW, CE
2
HIGH,
and WE LOW)
Write to the device by taking Chip Enable One (CE
1
) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE
2
) input
HIGH. Data on the eight IO pins (IO
0
through IO
7
) is then
written into the location specified on the address pins (A
0
through A
16
).
Read from the device by taking Chip Enable One (CE
1
) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE
2
) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the IO pins.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
IO0
IO1
ROW DECODER
128K x 8
ARRAY
SENSE AMPS
IO2
IO3
IO4
IO5
IO6
CE1
CE2
WE
OE
COLUMN DECODER
POWER
DOWN
IO7
Note
1. For guidelines on SRAM system design, please refer to the 鈥楽ystem Design Guidelines鈥?Cypress application note, available on the internet at
www.cypress.com.
A9
A10
A11
A12
A13
A14
A15
A16
Cypress Semiconductor Corporation
Document #: 38-05468 Rev. *E
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised February 22, 2007
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CY7C109D相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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