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CY7C107B-25VC Datasheet

  • CY7C107B-25VC

  • 1M x 1 Static RAM

  • 147.31KB

  • 9頁

  • CYPRESS

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07B
CY7C107B
CY7C1007B
1M x 1 Static RAM
Features
鈥?High speed
鈥?t
AA
= 12 ns
鈥?CMOS for optimum speed/power
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(D
IN
) is written into the memory location specified on the ad-
dress pins (A
0
through A
19
).
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (D
OUT
)
pin.
The output pin (D
OUT
) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
Functional Description
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
Logic Block Diagram
D
IN
Pin Configuration
SOJ
Top View
A
10
A
11
A
12
A
13
A
14
A
15
NC
A
16
A
17
A
18
A
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
512x2048
ARRA
Y
D
OUT
D
OUT
WE
GND
V
CC
A
9
A
8
A
7
A
6
A
5
A
4
NC
A
3
A
2
A
1
A
0
D
IN
CE
107B-2
COLUMN
DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
POWER
DOWN
SENSE AMPS
CE
WE
107B-1
Selection Guide
7C107B-12
7C1007B-12
12
90
2
7C107B-15
7C1007B-15
15
80
2
7C107B-20
7C1007B-20
20
75
2
7C107B-25
7C1007B-25
25
70
2
7C107B-35
7C1007B-35
35
60
2
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum CMOS Standby
Current SB2 (mA)
Cypress Semiconductor Corporation
Document #: 38-05030 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 7, 2001

CY7C107B-25VC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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