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CY7C1069DV33 Datasheet

  • CY7C1069DV33

  • 16-Mbit (2M x 8) Static RAM

  • 9頁

  • CYPRESS

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PRELIMINARY
CY7C1069DV33
16-Mbit (2M x 8) Static RAM
Features
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?I
CC
= 125 mA @ 10 ns
鈥?Low CMOS standby power
鈥?I
SB2
= 25 mA
鈥?Operating voltages of 3.3 鹵 0.3V
鈥?2.0V data retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
and CE
2
features
鈥?Available in Pb-free 54-pin TSOP II package and 48-ball
VFBGA packages
Functional Description
The CY7C1069DV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE
1
LOW, CE
2
HIGH, and WE
LOW).
The CY7C1069DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball very fine-pitch ball grid array (VFBGA) package.
Logic Block Diagram
INPUT BUFFER
Pin Configuration
TSOP II
Top View
NC
V
CC
NC
I/O
6
V
SS
I/O
7
A
4
A
3
A
2
A
1
A
0
NC
CE
1
V
CC
WE
CE
2
A
19
A
18
A
17
A
16
A
15
I/O
0
V
CC
I/O
1
NC
V
SS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
2M x 8
ARRAY
I/O
0
鈥揑/O
7
COLUMN
DECODER
WE
CE
2
OE
CE
1
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
NC
V
SS
NC
I/O
5
V
CC
I/O
4
A
5
A
6
A
7
A
8
A
9
NC
OE
V
SS
NC
A
20
A
10
A
11
A
12
A
13
A
14
I/O
3
V
SS
I/O
2
NC
ROW DECODER
SENSE AMPS
V
CC
NC
Selection Guide
鈥?0
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
10
125
25
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05478 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 14, 2006
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CY7C1069DV33相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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