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CY7C1062DV33 Datasheet

  • CY7C1062DV33

  • 16-Mbit (512K X 32) Static RAM

  • 10頁(yè)

  • CYPRESS

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PRELIMINARY
CY7C1062DV33
16-Mbit (512K X 32) Static RAM
Features
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?I
CC
= 150 mA @ 10 ns
鈥?Low CMOS standby power
鈥?I
SB2
= 25 mA
鈥?Operating voltages of 3.3 鹵 0.3V
鈥?2.0V data retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
, CE
2
, and CE
3
features
鈥?Available in Pb-free 119-ball plastic ball grid array
(PBGA) package
Functional Description
The CY7C1062DV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
Writing to the device is accomplished by enabling the chip
(CE
1,
CE
2
and CE
3
LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (B
A
) is LOW, then data from I/O
pins (I/O
0
through I/O
7
), is written into the location specified on
the address pins (A
0
through A
18
). If Byte Enable B (B
B
) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Likewise, B
C
and B
D
correspond with the I/O pins I/O
16
to I/O
23
and I/O
24
to I/O
31
, respectively.
Reading from the device is accomplished by enabling the chip
(CE
1,
CE
2
, and CE
3
LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (B
A
) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
Enable B (B
B
) is LOW, then data from memory will appear on
I/O
8
to I/O
15
. Similarly, B
c
and B
D
correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
The input/output pins (I/O
0
through I/O
31
) are placed in a
high-impedance state when the device is deselected (CE
1,
CE
2
or CE
3
HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (B
A-D
HIGH), or during a write
operation (CE
1,
CE
2
, and CE
3
LOW, and WE LOW).
The CY7C1062DV33 is available in 119-ball plastic ball grid
array (PBGA) package.
Logic Block Diagram
INPUT BUFFERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
512K x 32
ARRAY
OUTPUT BUFFERS
SENSE AMPS
WE
CE
1
CE
2
CE
3
OE
B
A
B
B
B
C
B
D
I/O
0
鈥揑/O
31
COLUMN
DECODER
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
Cypress Semiconductor Corporation
Document #: 38-05477 Rev.*C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 4, 2006
[+] Feedback
CONTROL LOGIC

CY7C1062DV33相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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