鈻?/div>
Functional Description
The CY7C1062DV33 is a high performance CMOS Static RAM
organized as 524,288 words by 32 bits.
To write to the device, take Chip Enables (CE
1,
CE
2,
and CE
3
LOW) and Write Enable (WE) input LOW. If Byte Enable A (B
A
)
is LOW, then data from IO pins (IO
0
through IO
7
) is written into
the location specified on the address pins (A
0
through A
18
). If
Byte Enable B (B
B
) is LOW, then data from IO pins (IO
8
through
IO
15
) is written into the location specified on the address pins (A
0
through A
18
). Likewise, B
C
and B
D
correspond with the IO pins
IO
16
to IO
23
and IO
24
to IO
31
, respectively.
To read from the device, take Chip Enables (CE
1,
CE
2
, and CE
3
LOW), and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If the first Byte Enable (B
A
) is LOW, then
data from the memory location specified by the address pins
appear on IO
0
to IO
7
. If Byte Enable B (B
B
) is LOW, then data
from memory appears on IO
8
to IO
15
. Likewise, B
c
and B
D
corre-
spond to the third and fourth bytes. For more information, see
Truth Table
on page 9 for a complete description of read and
write modes.
The input and output pins (IO
0
through IO
31
) are placed in a high
impedance state when the device is deselected (CE
1,
CE
2,
or
CE
3
HIGH), the outputs are disabled (OE HIGH), the byte selects
are disabled (B
A-D
HIGH), or during a write operation (CE
1,
CE
2
and CE
3
LOW, and WE LOW).
High speed
鉂?/div>
t
AA
= 10 ns
Low active power
鉂?/div>
I
CC
= 175 mA at 10 ns
Low CMOS standby power
鉂?/div>
I
SB2
= 25 mA
Operating voltages of 3.3 鹵 0.3V
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and CE
3
features
Available in Pb-free 119-Ball PBGA package
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Logic Block Diagram
WE
CE
1
CE
2
CE
3
OE
B
A
B
B
B
C
B
D
CONTROL LOGIC
INPUT BUFFERS
A
(9:0)
512K x 32
ARRAY
OUTPUT BUFFERS
ROW DECODER
SENSE AMPS
IO
0
鈥?IO
31
COLUMN
DECODER
A
(18:10)
Cypress Semiconductor Corporation
Document Number: 38-05477 Rev.*D
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 06, 2007
CY7C1062DV33_07相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
Cypress
-
英文版
16K x 16/18 Dual-Port Static RAM
Cypress
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
1
2
3
4
5
6
7
8
9
10
11
