CY7C1061BV33
16-Mbit (1M x 16) Static RAM
Features
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?990 mW (max.)
鈥?Operating voltages of 3.3 鹵 0.3V
鈥?2.0V data retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Available in Pb-free and non Pb-free 54-pin TSOP II
package
Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
19
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by enabling the chip
by taking CE LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. See the truth table at the back of this data sheet for a
complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW and WE LOW).
The CY7C1061BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Functional Description
The CY7C1061BV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip (CE
LOW) while forcing the Write Enable (WE) input LOW. If Byte
Logic Block Diagram
Pin Configurations
[1, 2]
54-pin TSOP II (Top View)
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
1M x 16
ARRAY
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
I/O
12
V
CC
I/O
13
I/O
14
V
SS
I/O
15
A
4
A
3
A
2
A
1
A
0
BHE
CE
V
CC
WE
DNU/V
CC
A
19
A
18
A
17
A
16
A
15
I/O
0
V
CC
I/O
1
I/O
2
V
SS
I/O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
I/O
11
V
SS
I/O
10
I/O
9
V
CC
I/O
8
A
5
A
6
A
7
A
8
A
9
NC
OE
V
SS
DNU/V
SS
BLE
A
10
A
11
A
12
A
13
A
14
I/O
7
V
SS
I/O
6
I/O
5
V
CC
I/O
4
ROW DECODER
Notes:
1. DNU/V
CC
Pin (#16) has to be left floating or connected to V
CC
and DNU/V
SS
Pin (#40) has to be left floating or connected to V
SS
to ensure proper application.
2. NC 鈥?No Connect Pins are not connected to the die
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05693 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised August 3, 2006
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