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CY7C1059DV33_07 Datasheet

  • CY7C1059DV33_07

  • 8-Mbit (1M x 8) Static RAM

  • 9頁(yè)

  • CYPRESS

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CY7C1059DV33
8-Mbit (1M x 8) Static RAM
Features
鈻?/div>
Functional Description
The CY7C1059DV33
[1]
is a high performance CMOS Static RAM
organized as 1M words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. To write to the device,
take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data
on the eight IO pins (IO
0
through IO
7
) is then written into the
location specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
The eight input or output pins (IO
0
through IO
7
) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW, and WE LOW).
The CY7C1059DV33 is available in 36-ball FBGA and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
High speed
鉂?/div>
t
AA
= 10 ns
Low active power
鉂?/div>
I
CC
= 110 mA at 10 ns
Low CMOS standby power
鉂?/div>
I
SB2
= 20 mA
2.0V data retention
Automatic power down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 44-pin TSOP II package
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
INPUT BUFFER
ROW DECODER
IO0
IO1
SENSE AMPS
IO2
IO3
IO4
IO5
IO6
1M x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO7
Note
1. For guidelines about SRAM system design, refer to the Cypress application note
AN1064, SRAM System Guidelines
available at
www.cypress.com.
A11
A12
A13
A14
A15
A16
A17
A18
A19
Cypress Semiconductor Corporation
Document #: 001-00061 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 26, 2007
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CY7C1059DV33_07相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
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  • 英文版
    32K x 8/9 Dual-Port Static RAM
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  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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