PRELIMINARY
CY7C1034DV33
6-Mbit (256K X 24) Static RAM
Features
鈥?High speed
鈥?t
AA
= 8 ns
鈥?Low active power
鈥?I
CC
= 185 mA @ 8 ns
鈥?Low CMOS standby power
鈥?I
SB2
= 25 mA
鈥?Operating voltages of 3.3 鹵 0.3V
鈥?2.0V data retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
, CE
2
and CE
3
features
鈥?Available in Pb-Free Standard 119-ball PBGA
Functional Description
The CY7C1034DV33 is a high-performance CMOS static
RAM organized as 256K words by 24 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
To write to the device, enable the chip (CE
1
LOW, CE
2
HIGH
and CE
3
LOW) while forcing the Write Enable (WE) input
LOW.
To read from the device, enable the chip by taking CE
1
LOW
CE
2
HIGH and CE
3
LOW while forcing the Output Enable (OE)
LOW and the Write Enable (WE) HIGH. See the truth table at
the back of this data sheet for a complete description of Read
and Write modes.
The 24 I/O pins (I/O
0
鈥揑/O
23
) are placed in a high-impedance
state when the device is deselected (CE
1
HIGH/CE
2
LOW/CE
3
HIGH) or when the output enable (OE) is HIGH
during a Write operation. (CE
1
LOW, CE
2
HIGH, CE
3
LOW
and WE LOW).
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
256K x 24
ARRAY
SENSE AMPS
I/O
0
鈥揑/O
23
COLUMN
DECODER
CONTROL LOGIC
CE
1
, CE
2
, CE
3
WE
OE
Selection Guide
鈥?
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
8
185
25
Unit
ns
mA
mA
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Cypress Semiconductor Corporation
Document #: 001-08351 Rev. *A
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 4, 2006
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