CY7C1021B
CY7C10211B
1-Mbit (64K x 16) Static RAM
Features
鈥?Temperature Ranges
鈥?Commercial: 0擄C to 70擄C
鈥?Industrial: 鈥?0擄C to 85擄C
鈥?Automotive: 鈥?0擄C to 125擄C
鈥?High speed
鈥?t
AA
= 10 ns (Commercial & Industrial)
鈥?t
AA
= 15 ns (Automotive)
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?825 mW (max.)
鈥?Automatic power-down when deselected
鈥?Independent control of upper and lower bits
鈥?Available in 44-pin TSOP II and 400-mil SOJ
鈥?Also available in Lead (Pb)-Free 44-pin TSOP II
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021B/10211B is available in standard 44-pin
TSOP Type II and 400-mil-wide SOJ packages. Customers
should use part number CY7C10211B when ordering parts
with 10-ns t
AA
, and CY7C1021B when ordering 12- and 15-ns
t
AA
.
Functional
Description
[1]
The CY7C1021B/10211B is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
512 X 2048
SENSE AMPS
I/O
1
鈥揑/O
8
I/O
9
鈥揑/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05145 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 20, 2004
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