PRELIMINARY
CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
鈥?High speed
鈥?t
AA
= 8 ns
鈥?Low active power
鈥?I
CC
= 185 mA @ 8 ns
鈥?Low CMOS standby power
鈥?I
SB2
= 25 mA
鈥?Operating voltages of 3.3 鹵 0.3V
鈥?2.0V data retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Available in Lead Pb-Free Standard 119-ball PBGA
power-down feature that significantly
consumption when deselected.
reduces
power
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A
0
鈥揂
18
). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
The 24 I/O pins (I/O
0
鈥揑/O
23
) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
Functional Description
The CY7C1012DV33 is a high-performance CMOS static
RAM organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE
1
, CE
2
,
CE
3
). CE
1
controls the data on the I/O
0
鈥揑/O
7
, while CE
2
controls the data on I/O
8
鈥揑/O
15
, and CE
3
controls the data on
the data pins I/O
16
鈥揑/O
23
. This device has an automatic
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
512K x 24
ARRAY
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
I/O
16
鈥揑/O
23
COLUMN
DECODER
CONTROL LOGIC
CE
1
, CE
2
, CE
3
WE
OE
Selection Guide
鈥?
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
8
185
25
Unit
ns
mA
mA
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
Cypress Semiconductor Corporation
Document #: 38-05610 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 4, 2006
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