鈻?/div>
Functional Description
The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE
1
, CE
2
, and CE
3
).
CE
1
controls the data on the IO
0
鈥?IO
7
, while CE
2
controls the
data on IO
8
鈥?IO
15
, and CE
3
controls the data on the data pins
IO
16
鈥?IO
23
. This device has an automatic power down feature
that significantly reduces power consumption when deselected.
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input and output (IO)
pins is then written into the location specified on the address pins
(A
0
鈥?A
18
). Asserting all of the chip selects LOW and write enable
LOW writes all 24 bits of data into the SRAM. Output enable (OE)
is ignored while in WRITE mode.
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select controlling that byte
is LOW and write enable (WE) HIGH, while output enable (OE)
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (IO) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 IO pins (IO
0
鈥?IO
23
) are placed in a high impedance state
when all the chip selects are HIGH or when the output enable
(OE) is HIGH during a READ mode. For more information, see
the
Truth Table
on page 8.
High speed
鉂?/div>
t
AA
= 8 ns
Low active power
鉂?/div>
I
CC
= 225 mA at 8 ns
Low CMOS standby power
鉂?/div>
I
SB2
= 25 mA
Operating voltages of 3.3 鹵 0.3V
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Available in Pb-free standard 119-Ball PBGA
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Logic Block Diagram
INPUT BUFFER
ROW DECODER
A
(9:0)
512K x 24
ARRAY
SENSE AMPS
IO
0
鈥?IO
7
IO
8
鈥?IO
15
IO
16
鈥?IO
23
COLUMN
DECODER
CONTROL LOGIC
CE
1
, CE
2
, CE
3
WE
OE
A
(18:10)
Cypress Semiconductor Corporation
Document Number: 38-05610 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 10, 2007
CY7C1012DV33_07相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠商
下載
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
Cypress
-
英文版
16K x 16/18 Dual-Port Static RAM
Cypress
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
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