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CY7C09349AV

CY7C09359AV

3.3V 4K/8K x 18

Synchronous Dual-Port Static RAM

Features

鈥?True dual-ported memory cells which allow simulta-

neous access of the same memory location

鈥?Two Flow-Through/Pipelined devices

鈥?4K x 18 organization (CY7C09349AV)

鈥?8K x 18 organization (CY7C09359AV)

鈥?Three Modes

鈥?Flow-Through

鈥?Pipelined

鈥?Burst

鈥?Pipelined output mode on both ports allows fast 83-MHz

operation

鈥?0.35-micron CMOS for optimum speed/power

v

鈥?High-speed clock to data access 9 and 12 ns (max.)

鈥?3.3V Low operating power

鈥?Active = 135 mA (typical)

鈥?Standby = 10

碌A(chǔ)

(typical)

鈥?Fully synchronous interface for easier operation

鈥?Burst counters increment addresses internally

鈥?Shorten cycle times

鈥?Minimize bus noise

鈥?/div>

鈥?Supported in Flow-Through and Pipelined modes

Dual Chip Enables for easy depth expansion

Upper and lower byte controls for bus matching

Automatic power-down

Commercial and Industrial temperature ranges

Available in 100-pin TQFP

Logic Block Diagram

R/W

L

UB

L

R/W

R

UB

R

CE

0L

CE

1L

LB

L

OE

L

1

0/1

1

0/1

0

CE

0R

CE

1R

LB

R

OE

R

FT/Pipe

L

9

0/1

1b 0b 1a 0a

b

a

0a 1a 0b 1b

a

b

0/1

FT/Pipe

R

9

I/O

9L

鈥揑/O

17L

9

I/O

9R

鈥揑/O

17R

I/O

Control

I/O

Control

9

I/O

0L

鈥揑/O

8L

A

0L

鈥揂

11/12L

CLK

L

ADS

L

CNTEN

L

CNTRST

L

[1]

I/O

0R

鈥揑/O

8R

12/13

Counter/

Address

Register

Decode

True Dual-Ported

RAM Array

Counter/

Address

Register

Decode

A

0R

鈥揂

11/12R

CLK

R

ADS

R

CNTEN

R

CNTRST

R

[1]

Notes:

1. A

0

鈥揂

11

for 4K; A

0

鈥揂

12

for 8K devices.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

鈥?/div>

CA 95134

鈥?/div>

408-943-2600

November 13, 2000

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