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CY7C0832V Datasheet

  • CY7C0832V

  • Memory

  • 32頁

  • ETC

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CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
Features
鈥?True dual-ported memory cells that allow simultaneous
access of the same memory location
鈥?Synchronous pipelined operation
鈥?Organization of 2M and 4.5M devices
鈥?128K 脳 36 (CY7C0852V)
鈥?64K 脳 36 (CY7C0851V)
鈥?256K 脳 18 (CY7C0832V)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?128K 脳 18 (CY7C0831V)
Pipelined output mode allows fast 167-MHz operation
0.18-micron CMOS for optimum speed and power
High-speed clock to data access: 4.0 ns (max.)
3.3V low operating power
鈥?Active = 225 mA (typical)
鈥?Standby = 55mA (typical)
Interrupt flags for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
172-ball BGA (1 mm pitch) (15 mm 脳 15 mm)
120-pin TQFP (14 mm 脳 14 mm 脳 1.4 mm)
176-pin TQFP (24 mm 脳 24 mm 脳 1.4 mm)
FLEx36錚?devices are footprint upgradeable from 2M to
4M to 9M
Counter wrap around control
鈥?Internal mask register controls counter wrap-around
鈥?Counter-interrupt flags to indicate wrap-around
鈥?Memory block retransmit operation
鈥?Counter readback on address lines
鈥?Mask register readback on address lines
鈥?Dual Chip Enables on both ports for easy depth
expansion
Functional Description
The CY7C0851V/CY7C0852V/CY7C0831VCY7C0832V are
2M and 4.5M pipelined, synchronous, true dual-port static
RAMs that are high-speed, low-power 3.3V CMOS. Two ports
are provided, permitting independent, simultaneous access for
Reads from any location in memory. A particular port can write
to a certain location while another port is reading that location.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address,
and data lines allow for minimal set-up and hold time.
During a Read operation, data is registered for decreased
cycle time. Clock to data valid t
CD2
= 4.0 ns at 167 MHz. Each
port contains a burst counter on the input address register.
After externally loading the counter with the initial address, the
counter will increment the address internally (more details to
follow). The internal Write pulse width is independent of the
duration of the R/W input signal. The internal Write pulse is
self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port鈥檚 burst counter is loaded when the port鈥檚
address strobe (ADS) and CNTEN signals are LOW. When the
port鈥檚 CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port鈥檚 clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap. The counter and mask register operations are described
in more detail in the following sections.
New features added to the CY7C0851V/CY7C0852V/
CY7C0831V/CY7C0832V devices include: readback of
burst-counter internal address value on address lines,
counter-mask registers to control the counter wrap-around,
counter interrupt (CNTINT) flags, readback of mask register
value on address lines, retransmit functionality, interrupt flags
for message passing, JTAG for boundary scan, and
asynchronous Master Reset (MRST).
Cypress offers an upgrade to a 9M synchronous Dual Port with
a compatible footprint. Please see the application note
Upgrading the 4-Meg (CY7C0852) Dual-Port to a 9-Meg
(CY7C0853) Dual-Port
for more details.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Cypress Semiconductor Corporation
Document #: 38-06059 Rev. *H
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised October 21, 2003

CY7C0832V相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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