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CY7C0430V Datasheet

  • CY7C0430V

  • 3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM

  • 37頁

  • CYPRESS

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30V
PRELIMINARY
CY7C0430V
3.3V 64K x 18
Synchronous QuadPort鈩?Static RAM
Features
鈥?True four-ported memory cells which allow simulta-
neous access of the same memory location
鈥?Synchronous Pipelined device
鈥?64K x 18 organization
鈥?Pipelined output mode allows fast 133-MHz operation
鈥?High Bandwidth up to 10 Gbps (133 MHz x 18 bits wide
x 4 ports)
鈥?0.25-micron CMOS for optimum speed/power
鈥?High-speed clock to data access 4.7 ns (max.)
鈥?3.3V Low operating power
鈥?Active = 750mA (maximum)
鈥?Standby = 1mA (maximum)
鈥?Counter wrap-around control
鈥?Internal mask register controls counter wrap-around
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Counter-Interrupt flags to indicate wrap-around
Counter readback on address lines
Mask register readback on address lines
Interrupt flags for message passing
Master reset for all ports
Width and depth expansion capabilities
Dual Chip Enables on all ports for easy depth expansion
Separate upper-byte and lower-byte controls on all
ports
272-BGA package (27 mm x 27 mm 1.27 mm ball pitch)
Commercial and Industrial temperature ranges
IEEE 1149.1 JTAG boundary scan
BIST (Built In Self Test) controller
Top Level Logic Block Diagram
Port 1 Operation-Control Logic Blocks
[1]
MRST
UB
P1
LB
P1
R/W
P1
OE
P1
CE
0P1
CE
1P1
CLK
P1
Reset
Logic
Port-1
Control
Logic
TMS
TCK
TDI
CLKBIST
BIST
JTAG
Controller
TDO
18
I/O
0P1
- I/O
17P1
CLK
P1
A
0P1
鈥揂
15P1
MKLD
P1
CNTLD
P1
CNTINC
P1
CNTRD
P1
MKRD
P1
CNTRST
P1
INT
P1
CNTINT
P1
16
Port 1
I/O
Port 4 Logic Blocks
[2]
Port 1
Counter/
Mask Reg/
Address
Decode
Port 1
Port 4
RAM
Array
Port 2
Port 3
Port 2 Logic Blocks
[2]
Port 3 Logic Blocks
[2]
Notes:
1. Port 1 Control Logic Block is detailed on page 2.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?408-943-2600
November 18, 1999

CY7C0430V相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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