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0.25-micron CMOS for optimum speed/power
鈥?IEEE 1149.1 JTAG boundary scan
鈥?Width and depth expansion capabilities
鈥?BIST (Built-In Self-Test) controller
鈥?Dual Chip Enables on all ports for easy depth expansion
鈥?Separate upper-byte and lower-byte controls on all
ports
鈥?Simple array partitioning (CY7C0430BV only)
鈥?Internal mask register controls counter wrap-around
鈥?Counter-Interrupt flags to indicate wrap-around
鈥?Counter and mask registers readback on address
鈥?272-ball BGA package (27-mm 脳 27-mm 脳 1.27-mm ball
pitch)
鈥?Commercial and industrial temperature ranges
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3.3V low operating power
鈥?Active = 750 mA (maximum)
鈥?Standby = 15 mA (maximum
QuadPort DSE Family Applications
PORT 1
PORT 3
PORT 2
PORT 4
BUFFERED SWITCH
PORT 2
PORT 1
PORT 3
PORT 4
REDUNDANT DATA MIRROR
Note:
1. f
MAX2
for commercial is 135 MHz and for industrial is 133 MHz.
Cypress Semiconductor Corporation
Document #: 38-06027 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised May 14, 2002
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