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CY7C024V Datasheet

  • CY7C024V

  • 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

  • 20頁

  • CYPRESS

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1
PRELIMINARY
CY7C024V/025V/026V
CY7C0241V/0251V/036V
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Features
鈥?True dual-ported memory cells which allow simulta-
neous access of the same memory location
鈥?4/8/16K x 16 organization (CY7C024V/025V/026V)
鈥?4/8K x 18 organization (CY7C0241V/0251V)
鈥?16K x 18 organization (CY7C036V)
鈥?0.35-micron CMOS for optimum speed/power
鈥?High-speed access: 15
[1]
/20/25 ns
鈥?Low operating power
鈥?/div>
Active: I
CC
= 115 mA (typical)
鈥?Standby: I
SB3
= 10
碌A
(typical)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
鈥?On-chip arbitration logic
鈥?Semaphores included to permit software handshaking
between ports
鈥?INT flag for port-to-port communication
鈥?Separate upper-byte and lower-byte control
鈥?Pin select for Master or Slave
鈥?Commercial and industrial temperature ranges
鈥?Available in 100-pin TQFP
鈥?Pin-compatible and functionally equivalent to
IDT70V24, 70V25, and 7V0261.
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
L
LB
L
OE
L
CE
R
LB
R
OE
R
[2]
8/9
8/9
8/9
[2]
I/O
8/9L
鈥揑/O
15/17L
[3]
I/O
0L
鈥揑/O
7/8L
I/O
Control
I/O
Control
8/9
I/O
8/9L
鈥揑/O
15/17R
[3]
I/O
0L
鈥揑/O
7/8R
[4]
12/13/14
A
0L
鈥揂
11/1213L
Address
Decode
12/13/14
True Dual-Ported
RAM Array
Address
Decode
12/13/14
12/13/14
[4]
A
0R
鈥揂
11/12/13R
A
0L
鈥揂
11/12/13L
CE
L
OE
L
R/W
L
SEM
L
[5]
[4]
Interrupt
Semaphore
Arbitration
A
0R
鈥揂
11/12/13R
CE
R
OE
R
R/W
R
SEM
R
[5]
[4]
BUSY
L
INT
L
UB
L
LB
L
Notes:
1. Call for availability.
2. I/O
8
鈥揑/O
15
for x16 devices; I/O
9
鈥揑/O
17
for x18 devices.
3. I/O
0
鈥揑/O
7
for x16 devices; I/O
0
鈥揑/O
8
for x18 devices.
4. A
0
鈥揂
11
for 4K devices; A
0
鈥揂
12
for 8K devices; A
0
鈥揂
13
for 16K devices.
5. BUSY is an output in master mode and an input in slave mode.
M/S
BUSY
R
INT
R
UB
R
LB
R
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
October 18, 1999

CY7C024V相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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