RoboClock
廬
CY7B9973V
High-Speed Multi-Output PLL Clock Buffer
Features
鈥?10-MHz 鈥?200-MHz output operation
鈥?Output-to-output skews < 350 ps
鈥?13 LVTTL 50% duty-cycle outputs capable of driving
50惟 terminated lines
鈥?Phase-locked loop (PLL) LOCK indicator
鈥?3.3V LVTTL/LV differential (LVPECL) hot insertable
reference inputs
鈥?Multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20):(2, 4, 6,
8, 10, 12, 16, 20)
鈥?Operation with outputs operating at up to 10x input
frequency
鈥?Low cycle-to-cycle jitter (<
鹵75
ps peak-peak)
鈥?Single 3.3V 鹵 10% supply
鈥?Pin-compatible with Motorola MPC973
鈥?52-pin TQFP package
Functional Description
The CY7B9973V Low-Voltage PLL Clock Buffer offers
user-selectable frequency control over system clock functions.
This twelve output clock driver provides the system integrator
selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2,
5:3, 6:1 and 6:5 between outputs. An additional output is
dedicated to providing feedback information to allow the
internal PLL to multiply an external reference frequency by 4,
6, 8, 10, 12, 16 or 20. The completely integrated PLL reduces
jitter and simplifies board layout.
The thirteen configurable outputs can each drive terminated
transmission lines with impedances as low as 50惟 while deliv-
ering minimal and specified output skews at LVTTL levels.
The CY7B9973V has a flexible reference input scheme with
three different hot-insertion capable inputs. These inputs allow
the use of either differential LVPECL or single-ended LVTTL
inputs which can be dynamically selected to provide the
reference frequency.
Logic Diagram
PECL_CLK (11)
PECL_CLK (12)
PLL_En (6)
Ref_Sel (7)
TCLK_Sel (8)
1
LOCK (25)
Qa0 (50)
0
D Q
TCLK0 (9)
TCLK1 (10)
0
0
1
梅2/梅1
Qa1 (48)
Qa2 (46)
Qa3 (44)
Qb0 (38)
PHASE
DETECTOR
VCO
LPF
1
Ext_FB (31)
VCO_Sel (52)
D Q
Qb1 (36)
Qb2 (34)
fselFB2 (5)
MR/OE (2)
Reset
梅4, 梅6, 梅8, 梅12
梅4, 梅6, 梅8, 梅10
梅2, 梅4, 梅6, 梅8
D Q
Qb3 (32)
Qc0 (23)
Qc1 (21)
fsela0:1 (43,42)
fselb0:1 (41,40)
fselc0:1 (20,19)
fselFB0:1 (27,26)
2
2
2
2
D Q
Qc2 (18)
Qc3 (16)
梅4, 梅6, 梅8, 梅10
Data Generator
0
梅2
1
D Q
QFB (29)
Inv_Clk (14)
Cypress Semiconductor Corporation
Document #: 38-07430 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised September 27, 2006
[+] Feedback
1
2
3
4
5
6
7
8
