鈦?/div>
4
input frequency
1
1
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50鈩?while delivering minimal and specified output skews
and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to
鹵6
time units from their nominal 鈥渮ero鈥?skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this 鈥渮ero delay鈥?capability of the
LVPSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to
鹵12
time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input to output delay
50% duty-cycle outputs
LVTTL Outputs drive 50鈩?terminated lines
Operates from a single 3.3V supply
Low operating current
32-pin PLCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Functional Description
The CY7B991V Low Voltage Programmable Skew Clock Buff-
er (LVPSCB) offers user-selectable control over system clock
Logic Block Diagram
TEST
Pin Configuration
PLCC
3F0
2F1
FS
FILTER
REF
FS
4F0
4F1
4
3F1
4Q0
SELECT
INPUTS
(THREE
LEVEL)
4Q1
V
CCQ
SKEW
3Q0
3Q1
SELECT
2Q0
MATRIX
2Q1
1Q0
1Q1
7B991V鈥?
3
2
1
5
6
7
8
9
10
11
12
32 31 30
29
28
27
26
TEST
V
CCQ
GND
REF
FB
PHASE
FREQ
DET
VCO AND
TIME UNIT
GENERATOR
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
4F0
4F1
3F0
3F1
V
CCN
4Q1
4Q0
GND
GND
CY7B991V
25
24
23
22
2F0
2F1
13
21
14 15 16 17 18 19 20
3Q1
3Q0
FB
2Q1
V
CCN
V
CCN
2Q0
1F0
1F1
7B991V鈥?
Cypress Semiconductor Corporation
Document #: 38-07141 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 24, 2001
CY7B991V-2JC 產(chǎn)品屬性
CY7B991V
30
集成電路 (IC)
時鐘/計時 - 時鐘緩沖器，驅(qū)動器
RoboClock™
緩沖器/驅(qū)動器
1
8:8
是/是
三態(tài)
LVTTL
80MHz
2.97 V ~ 3.63 V
0°C ~ 70°C
表面貼裝
32-LCC（J 形引線）
32-PLCC（13.97x11.43）
管件
428-1382
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