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CY74FCT480BTQC Datasheet

  • CY74FCT480BTQC

  • FCT SERIES, 8-BIT PARITY GENERATOR/CHECKER, TRUE OUTPUT, PDS...

  • 8頁(yè)

  • TI

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1CY54/74FCT480T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY54/74FCT480T
SCCS025 - May 1993 - Revised March 2000
Dual 8-Bit Parity Generator/Checker
鈥?/div>
Two 8-bit parity generator/checkers
鈥?/div>
Open drain Active LOW parity error output
鈥?/div>
Expandable for larger word widths
Features
鈥?/div>
Function, pinout and drive compatible with FCT and F
logic
鈥?/div>
FCT-A speed at 7.5 ns max. (Com鈥檒)
FCT-B speed at 5.6 ns max. (Com鈥檒)
鈥?/div>
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?/div>
Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?/div>
Power-off disable feature
鈥?/div>
Matched rise and fall times
鈥?/div>
ESD > 2000V
鈥?/div>
Fully compatible with TTL input and output logic levels
鈥?Sink Current
64 mA (Com鈥檒),
32 mA (Mil)
Source Current 32 mA (Com鈥檒),
12 mA (Mil)
Functional Description
The FCT480T is a high-speed dual 8-bit parity
generator/checker. Each parity generator/checker accepts
eight data bits and one parity bit as inputs, and generates a
sum and parity error output. The FCT480T can be used in
ODD parity systems. The parity error output is open-drain,
designed for easy expansion of the word width by a wired-OR
connection of several FCT480T type devices. Since additional
logic is not needed, the parity generation or checking times
remain the same as for an individual FCT480T device.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
A
1
B
1
C
1
D
1
E
1
F
1
G
1
H
1
PAR
1
CHK/GEN
A
2
B
2
C
2
D
2
E
2
F
2
G
2
H
2
PAR
2
FCT480T鈥?
ERR
ODD
1
ODD
2
Pin Configurations
DIP/SOIC/QSOP
Top View
LCC
Top View
E1
D1
A
1
B
1
C
1
D
1
C
1
B
1
A
1
NC
V
CC
A
2
B
2
E
1
F
1
G
1
H
1
PAR
1
CHK/GEN
ODD
1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
2
B
2
C
2
D
2
E
2
F
2
G
2
H
2
PAR
2
ERROR
ODD
2
FCT480T
鈥?
CHK/GEN
ODD
1
GND
NC
ODD
2
ERROR
PAR
2
11 10 9 8 7 6 5
12
4
13
3
14
2
1
15
16
28
17
27
18
26
19 20 21 22 23 24 25
H2
G2
F2
NC
E2
D2
C2
PAR1
H1
G1
NC
F1
FCT480T
鈥?
Copyright
漏
2000, Texas Instruments Incorporated

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