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CY74FCT377T Datasheet

  • CY74FCT377T

  • Octal D-Type Flip-Flops with Enable

  • 8頁

  • ETC

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CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
SCCS023A 鈥?MAY 1994 鈥?REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
D
D
D
description
The 鈥橣CT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common
buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE) input is low. The register
is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is
transferred to the corresponding flip-flop output (O). CE must be stable only one setup time prior to the
low-to-high clock transition for predictable operation.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
錚?/div>
2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
O
3
GND
CP
O
4
D
4
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced V
OH
(Typically = 3.3 V) Versions of
Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
I
off
Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and
Output Logic Levels
Clock Enable for Address and Data
Synchronization Application
Eight Edge-Triggered D-Type Flip-Flops
CY54FCT377T
鈥?32-mA Output Sink Current
鈥?12-mA Output Source Current
CY74FCT377T
鈥?64-mA Output Sink Current
鈥?32-mA Output Source Current
SN74FCT377T . . . Q OR SO PACKAGE
(TOP VIEW)
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
SN54FCT377T . . . L PACKAGE
(TOP VIEW)
CE
V
CC
D
0
O
0
D
1
O
1
O
2
D
2
D
3
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
O
7
D
7
D
6
O
6
O
5
D
5
1

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