音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CY74FCT273ATSOC Datasheet

  • CY74FCT273ATSOC

  • Texas Instruments [8-Bit Register]

  • TI

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY54/74FCT273T
SCCS020 - March 1995 - Revised February 2000
8-Bit Register
Functional Description
The FCT273T consists of eight edge-triggered D-type
鏗俰p-鏗俹ps with individual D inputs and Q outputs. The common
buffered clock (CP) and master reset (MR) load and reset all
鏗俰p-鏗俹ps simultaneously. The FCT273T is an edge-triggered
register. The state of each D input (one set-up time before the
LOW-to-HIGH clock transition) is transferred to the corre-
sponding 鏗俰p-鏗俹p鈥檚 Q output. All outputs will be forced LOW by
a low voltage level on the MR input.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Features
鈥?Function, pinout, and drive compatible with FCT and
F logic
鈥?FCT-C speed at 5.8 ns max. (Com鈥檒)
FCT-A speed at 7.2 ns max. (Com鈥檒)
鈥?Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?Power-off disable feature
鈥?Matched rise and fall times
鈥?ESD > 2000V
鈥?Fully compatible with TTL input and output logic levels
鈥?Extended commercial range of
鈭?0藲C
to +85藲C
鈥?Sink current
64 mA (Com鈥檒), 32 mA (Mil)
Source current
32 mA (Com鈥檒), 12 mA (Mil)
Logic Block Diagram
D
0
CP
D
CP
R
D
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
FCT273T鈥?
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Pin Configurations
LCC
Top View
D3
D2
Q2
Q1
D1
MR
Q
0
3
2
1
20
19
14 1516 17 18
D
5
Q5
Q6
D
6
D
7
D
0
Q
0
MR
V
CC
Q
7
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
GND
Logic Symbol
DIP/SOIC/QSOP
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q
7
D
7
D
6
Q
6
Q
5
D
5
D
4
Q
4
CP
8 7 6 5 4
Q
3
GND
CP
Q
4
D
4
9
10
11
12
13
D
0
CP
MR
Q
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
FCT273T鈥?
FCT273T鈥?
FCT273T鈥?
Function Table
[1]
Operating Mode
Reset (clear)
Load 鈥?鈥?/div>
Load 鈥?鈥?/div>
Note:
1. H
h
L
l
X
MR
L
H
H
Inputs
CP
X
D
X
h
l
Output
Q
L
H
L
= HIGH Voltage Level steady state
= HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition
= LOW Voltage Level steady state
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition
= Don鈥檛 Care
= LOW-to-HIGH clock transition
Copyright
漏
2000, Texas Instruments Incorporated

CY74FCT273ATSOC PDF文件相關(guān)型號(hào)

CY74FCT273ATSOCT,CY74FCT273CTQCT,CY74FCT273CTSOC,CY74FCT273CTSOCT

CY74FCT273ATSOC 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74FCT

  • 主復(fù)位

  • D 型總線

  • 非反相

  • 1

  • 8

  • -

  • 2ns

  • 正邊沿

  • 32mA，64mA

  • 4.75 V ~ 5.25 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 管件

CY74FCT273ATSOC相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！