1CY54/
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT2652T
SCCS044 - May 1994 - Revised March 2000
8-Bit Registered Transceiver
mission of data directly from the input bus or from the internal
storage registers. GAB and GBA control pins are provided to
control the transceiver functions. SAB and SBA control pins are
provided to select either real-time or stored data transfer.
The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during transition
between stored and real-time data. A LOW input level selects
real-time data and a HIGH selects stored data. Data on the A
or B data bus, or both, can be stored in the internal D 鏗俰p-鏗俹ps
by LOW-to-HIGH transitions at the appropriate clock pins
(CPAB or CPBA), regardless of the select or enable control
pins. When SAB and SBA are in the real-time transfer mode,
it is also possible to store data without using the internal
D-type 鏗俰p-鏗俹ps by simultaneously enabling GAB and GBA. In
this configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high imped-
ance, each set of bus lines will remain at its last state.
On-chip termination resistors are added to the outputs to
reduce system noise caused by re鏗俥ctions. The FCT2652T
can replace the FCT652T to reduce noise in existing designs.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards
Features
鈥?/div>
Function and pinout compatible with FCT and F logic
鈥?/div>
FCT-C speed at 5.4 ns max. (Com鈥檒)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
FCT-A speed at 6.3 ns max. (Com鈥檒)
25鈩?output series resistors to reduce transmission line
re鏗俥ction noise
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
Fully compatible with TTL input and output logic levels
Sink current
12 mA
Source current
15 mA
ESD > 2000V
Independent register for A and B buses
Multiplexed real-time and stored data transfer
Extended commercial temp. range of 鈥?0藲C to +85藲C
Functional Description
The FCT2652T consists of bus transceiver circuits, D-type
鏗俰p-鏗俹ps, and control circuitry arranged for multiplexed trans-
LogicBlockDiagram
CPBA
GAB
SBA
SAB
GBA
CPAB
B REG
1 OF8 CHANNELS
D
C
A
1
A REG
D
C
B
1
Pin Configurations
SOIC/QSOP
Top View
CPAB
SAB
GAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPBA
SBA
GBA
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
FCT2652T鈥?
TO 7 OTHERCHANNELS
FCT2652T
鈥?
Copyright
漏
2000, Texas Instruments Incorporated
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