Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT2543T
SCCS042 - September 1994 - Revised March 2000
8-Bit Latched Transceiver
Functional Description
The FCT2543T Octal Latched Tranceiver contains two sets of
eight D-type latches. Separate Latch Enable (LEAB, LEBA)
and Output Enable (OEAB, OEBA) permits each latch set to
have independent control of inputting and outputting in either
direction of data 鏗俹w. For data 鏗俹w from A to B, for example,
the A-to-B Enable (CEAB) input must be LOW to enter data
from A or to take data from B, as indicated in the truth table.
With CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subse-
quent LOW-to-HIGH transition of the LEAB signal puts the A
latches in the storage mode and their output no longer change
with the A inputs. With CEAB and OEAB both LOW, the
three-state B output buffers are active and re鏗俥ct data present
at the output of the A latches. Control of data from B to A is
similar, but uses CEAB, LEAB, and OEAB inputs. On-chip ter-
mination resistors have been added to the outputs to reduce
system noise caused by re鏗俥ctions. The FCT2543T can be
used to replace the FCT543T to reduce noise in an existing
design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Features
鈥?/div>
Function and pinout compatible with FCT and F logic
鈥?/div>
FCT-C speed at 5.3 ns max.
FCT-A speed at 6.5 ns max.
鈥?/div>
25鈩?output series resistors to reduce transmission line
re鏗俥ction noise
鈥?/div>
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?/div>
Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?/div>
Power-off disable feature
鈥?/div>
Matched rise and fall times
鈥?/div>
Fully compatible with TTL input and output logic levels
鈥?Sink current
12 mA
Source current
15 mA
鈥?Separation controls for data 鏗俹w in each direction
鈥?/div>
Back to back latches for storage
鈥?ESD > 2000V
鈥?Extended commercial temp. range of 鈥?0藲C to +85藲C
Functional Block Diagram
Pin Configurations
Detail A
D Q
LE
A
0
Q D
LE
LEBA
OEBA
A
0
A
1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
OEBA
OEAB
CEBA
CEAB
LEBA
LEAB
FCT2543T
鈥?
Detail A x 7
B
1
B
2
B
3
B
4
B
5
B
6
B
7
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
GND
B
0
SOIC/QSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
LEAB
OEAB
FCT2543T
鈥?
Copyright
漏
2000, Texas Instruments Incorporated
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