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CY74FCT16500T_08 Datasheet

  • CY74FCT16500T_08

  • 18-Bit Registered Transceivers

  • 12頁

  • TI

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Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT16500T
CY74FCT162500T
SCCS056A - August 1994 - Revised October 2001
18-Bit Registered Transceivers
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched, or clock modes by combining D-type
latches and D-type 鏗俰p-鏗俹ps. Data 鏗俹w in each direction is
controlled by output-enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA)
inputs. For A-to-B data 鏗俹w, the device operates in transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/鏗俰p-鏗俹p on the
HIGH-to-LOW transition of CLKAB. OEAB performs the output
enable function on the B port. Data 鏗俹w from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA.
This device is fully speci鏗乪d for partial-power-down
applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current back鏗俹w through the device
when it is powered down.
The CY74FCT16500T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162500T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162500T is ideal for driving transmission lines.
SSOP/TSSOP
Top View
OEAB
LEAB
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLKBA
GND
Features
鈥?FCT-C speed at 4.6 ns
鈥?I
off
supports partial-power- mode operation
鈥?Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?Typical output skew < 250 ps
鈥?ESD > 2000V
鈥?TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
鈥?Industrial temperature range of
鈭?0藲C
to +85藲C
鈥?V
CC
= 5V
鹵
10%
CY74FCT16500T Features:
鈥?64 mA sink current, 32 mA source current
鈥?Typical V
OLP
(ground bounce) <1.0V at V
CC
= 5V,
T
A
= 25藲C
CY74FCT162500T Features:
鈥?Balanced 24 mA output drivers
鈥?Reduced system switching noise
鈥?Typical V
OLP
(ground bounce) <0.6V at V
CC
= 5V,
T
A
= 25藲C
Logic Block Diagram
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
C
C
B
1
D
A
8
A
9
A
10
A
11
A
12
GND
C
D
C
D
A
13
A
14
A
15
V
CC
A
16
A
17
TO 17 OTHER CHANNELS
FCT16500-1
GND
A
18
OEBA
LEBA
A
1
D
FCT16500-2
Copyright
漏
2001, Texas Instruments Incorporated

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