Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT163374
CY74FCT163H374
SCCS050 - March 1997 - Revised March 2000
16-Bit Registers
Functional Description
These devices are 16-bit D-type registers designed for use as
buffered registers in high-speed, low power bus applications.
These devices can be used as two independent 8-bit registers
or as a single 16-bit register by connecting the output Enable
(OE) and Clock (CLK) inputs. The outputs are 24-mA balanced
output drivers with current limiting resistors to reduce the need
for external terminating resistors, and provide for minimal
undershoot and reduced ground bounce. Flow-through pinout
and small shrink packaging aid in simplifying board layout.
The CY74FCT163H374 has 鈥渂us hold鈥?on the data inputs,
which retains the input鈥檚 last state whenever the source driving
the input goes to high impedance. This eliminates the need for
pull-up/down resistors and prevents 鏗俹ating inputs.
The CY74FCT163374 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.
Features
鈥?Low power, pin-compatible replacement for LCX and
LPT families
鈥?5V tolerant inputs and outputs
鈥?24 mA balanced drive outputs
鈥?Power-off disable outputs permits live insertion
鈥?Edge-rate control circuitry for reduced noise
鈥?FCT-C speed at 5.2 ns
鈥?Latch-up performance exceeds JEDEC standard no. 17
鈥?Typical output skew < 250 ps
鈥?Industrial temperature range of 鈥?0藲C to +85藲C
鈥?TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
鈥?Typical Volp (ground bounce) performance exceeds Mil
Std 883D
鈥?V
CC
= 2.7V to 3.6V
鈥?ESD (HBM) > 2000V
CY74FCT163H374
鈥?Bus hold on data inputs
鈥?Eliminates the need for external pull-up or pull-down
resistors
鈥?Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Logic Block Diagrams CY74FCT163374, CY74FCT163H374
Pin Configuration
SSOP/TSSOP
Top View
1
OE
1
O
1
1
O
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
CLK
1
D
1
1
D
2
1
OE
2
OE
GND
1
O
3
1
O
4
V
CC
1
O
5
2
O
1
1
O
6
GND
1
D
3
1
D
4
1
CLK
1
D
1
2
CLK
D
1
O
1
2
D
1
D
C
V
CC
1
D
5
1
D
6
C
GND
1
O
7
1
O
8
2
O
1
GND
1
D
7
1
D
8
2
D
1
2
D
2
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2
O
2
GND
2
O
3
2
O
4
V
CC
2
O
5
2
O
6
GND
2
D
3
2
D
4
V
CC
2
D
5
2
D
6
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
CLK
Lite Drive is a trademark of Cypress Semiconductor Corporation.
Copyright
漏
2000, Texas Instruments Incorporated
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