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CY62167DV30 Datasheet

  • CY62167DV30

  • 16-Mbit (1M x 16) Static RAM

  • 12頁

  • CYPRESS

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CY62167DV30
MoBL
錚?/div>
16-Mbit (1M x 16) Static RAM
Features
鈥?Very high speed: 55 ns
鈥?Wide voltage range: 2.20V 鈥?3.60V
鈥?Ultra-low active power
鈥?Typical active current: 2 mA @ f = 1 MHz
鈥?Typical active current: 15 mA @ f = f
max
鈥?Ultra-low standby power
鈥?Easy memory expansion with CE
1
, CE
2
, and OE
features
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
鈥?Packages offered in a 48-ball BGA and 48-pin TSOPI
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE
1
HIGH or CE
2
LOW or both BHE and BLE are
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a Write operation (CE
1
LOW, CE
2
HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
19
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
Functional
Description
[1]
The CY62167DV30 is a high-performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life錚?(MoBL
錚?/div>
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DATA IN DRIVERS
ROW DECODER
1M 脳 16
RAM Array
SENSE AMPS
I/O0 鈥?I/O7
I/O8 鈥?I/O15
COLUMN DECODER
BHE
WE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
CE
2
CE
1
Power-down
Circuit
BHE
BLE
CE
2
CE
1
Note:
1. For best-practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05328 Rev. *E
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 21, 2004

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