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CY62157CV30LL-55BAI Datasheet

  • CY62157CV30LL-55BAI

  • 512K x 16 Static RAM

  • 13頁

  • CYPRESS

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CY62157CV25/30/33
MoBL鈩?/div>
512K x 16 Static RAM
Features
鈥?High speed
鈥?55 ns and 70 ns availability
鈥?/div>
Voltage range:
鈥?CY62157CV25: 2.2V鈥?.7V
鈥?CY62157CV30: 2.7V鈥?.3V
鈥?CY62157CV33: 3.0V鈥?.6V
鈥?Ultra-low active power
鈥?Typical active current: 1.5 mA @ f = 1 MHz
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Typical active current: 5.5 mA @ f = f
max
(70 ns speed)
Low standby power
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
reducing power consumption by more than 99% when dese-
lected (CE
1
HIGH or CE
2
LOW or both BLE and BHE are
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE
1
HIGH or
CE
2
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O
0
through I/O
7
), is written into the location speci-
fied on the address pins (A
0
through A
18
). If Byte High Enable
(BHE) is LOW, then data from I/O pins (I/O
8
through I/O
15
) is
written into the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW and Chip Enable
2 (CE
2
) HIGH while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O
0
to
I/O
7
. If Byte High Enable (BHE) is LOW, then data from mem-
ory will appear on I/O
8
to I/O
15
. See the truth table at the back
of this data sheet for a complete description of read and write
modes.
The CY62157CV25/30/33 are available in a 48-ball FBGA
package.
Functional Description
The CY62157CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This is ideal for providing More Battery Life鈩?(MoBL鈩?
in portable applications such as cellular telephones. The de-
vices also have an automatic power-down feature that signifi-
cantly reduces power consumption by 80% when addresses
are not toggling. The device can also be put into standby mode
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DATA IN DRIVERS
ROW DECODER
512K 脳 16
RAM Array
2048 脳 4096
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
BHE
WE
OE
BLE
CE
2
CE
1
Power-down
Circuit
BHE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document #: 38-05014 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised April 23, 2002

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