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CY62146CV30LL-55BVI Datasheet

  • CY62146CV30LL-55BVI

  • 256K x 16 Static RAM

  • 12頁(yè)

  • CYPRESS

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CY62146CV30 MoBL鈩?/div>
256K x 16 Static RAM
Features
鈥?High speed:
鈥?55 ns and 70 ns availability
鈥?Voltage range:
鈥?CY62146CV30: 2.7V 鈥?3.3V
鈥?Pin compatible with CY62146V
鈥?Ultra-low active power
鈥?Typical active current: 1.5 mA @ f = 1 MHz
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Typical active current: 7 mA @ f = f
max
(70 ns speed)
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by 99% when deselected (CE
HIGH). The input/output pins (I/O
0
鈥?I/O
15
) are placed in a
high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a Write
operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
鈥?I/O
7
), is written
into the location specified on the address pins (A
0
鈥?A
17
). If
Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
鈥?I/O
15
) is written into the location specified on the
address pins (A
0
鈥?A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
鈥?I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the Truth Table on page 9 for a complete description of Read
and Write modes.
The CY62146CV30 is available in 48-ball FBGA packaging.
Functional Description
The CY62146CV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life鈩?(MoBL鈩? in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K 脳 16
RAM Array
2048 脳 2048
SENSE AMPS
I/O
0
鈥?I/O
7
I/O
8
鈥?I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 38-05203 Rev. **
鈥?/div>
3901 North First Street
A
14
A
15
A
16
A
17
A
11
A
12
A
13
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 17, 2001

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