CY62138CV25/30/33 MoBL
廬
CY62138CV MoBL
廬
2M (256K x 8) Static RAM
Features
鈥?Very high speed: 55 ns and 70 ns
鈥?Voltage range:
鈥?CY62138CV25: 2.2V鈥?.7V
鈥?CY62138CV30: 2.7V鈥?.3V
鈥?CY62138CV33: 3.0V鈥?.6V
鈥?CY62138CV: 2.7V鈥?.6V
鈥?Pin-compatible with CY62138V
鈥?Ultra low active power
鈥?Typical active current: 1.5 mA @ f = 1 MHz
鈥?Typical active current: 5.5 mA @ f = f
max
(70-ns
speed)
Low standby power
Easy memory expansion with CE
1
, CE
2
, and OE
features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 36-ball FBGA
bits. This device features advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Life鈩?(MoBL
廬
) in portable applications. The device also has
an automatic power-down feature that significantly reduces
power consumption by 80% when addresses are not toggling.
The device can be put into standby mode reducing power
consumption by more than 99% when deselected (CE
1
HIGH
or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable 2 (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
See the truth table at the back of this data sheet for a complete
description of read and write modes.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Functional Description
[1]
The CY62138CV25/30/33 and CY62138CV are high-perfor-
mance CMOS static RAMs organized as 256K words by eight
Logic Block Diagram
Data in Drivers
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
CE
1
CE
2
WE
OE
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
256K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05200 Rev. *D
鈥?/div>
3901 North First Street
A
12
A
13
A
14
A
15
A
16
A
17
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 20, 2002
CY62138CV30LL-55BAI相關(guān)型號PDF文件下載
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型號
版本
描述
廠商
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