CY62136V MoBL
廬
2-Mbit (128K x 16) Static RAM
Features
鈥?Temperature Ranges
鈥?Commercial : 0擄C to 70擄C
鈥?Industrial :
鈭?0擄C
to 85擄C
鈥?Automotive :
鈭?0擄C
to 125擄C
鈥?High speed: 55 ns and 70 ns
鈥?70-ns speed bin offered in both Industrial and
Automotive grades
鈥?Wide voltage range: 2.7V-3.6V
鈥?Ultra-low active, standby power
鈥?Easy memory expansion with CE and OE features
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
鈥?Package available in a standard 44-pin TSOP Type II
(forward pinout) package
This is ideal for providing More Battery Life鈩?(MoBL
廬
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
[1]
The CY62136V is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
128K x 16
RAM Array
2048 x 1024
SENSE AMPS
I/O
0
鈥?I/O
7
I/O
8
鈥?I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
12
A
11
A
13
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
A
14
A
15
A
16
Cypress Semiconductor Corporation
Document #: 38-05087 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised September 24, 2004
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