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CY62128BLL-70ZRC Datasheet

  • CY62128BLL-70ZRC

  • x8 SRAM

  • 12頁

  • ETC

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CY62128B MoBL鈩?/div>
128K x 8 Static RAM
1CY62128B MoBL鈩?/div>
Features
鈥?4.5V鈥?.5V operation
鈥?CMOS for optimum speed/power
鈥?Low active power (70 ns, LL version)
鈥?82.5 mW (max.) (15 mA)
鈥?Low standby power (70 ns, LL version)
鈥?110
碌W
(max.) (15
碌A(chǔ))
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
, CE
2
, and OE options
and three-state drivers. This device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
1
) and Write Enable (WE) inputs LOW and Chip En-
able Two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Functional Description
The CY62128B is a high-performance CMOS static RAM or-
ganized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE
1
), an active
HIGH Chip Enable (CE
2
), an active LOW Output Enable (OE),
Logic Block Diagram
Pin Configurations
Top View
SOIC
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O 0
I/O 1
SENSE AMPS
I/O 2
I/O 3
I/O 4
I/O 5
POWER
DOWN
512x 256x 8
ARRAY
CE1
CE2
WE
OE
COLUMN
DECODER
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
I/O 6
I/O 7
62128-1
1
2
3
4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GN
G
ND 16
G
g
gnc
NC
A16
A14
A12
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A
16
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
A
12
A
14
A
7
A
4
A
5
A
6
NC
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Reverse TSOP I
Top View
(not to scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
3
A
11
A
2
A
9
A
1
A
8
A
13
A
0
I/O
0
WE
I/O
1
CE
2
A
15
I/O
2
GND V
CC
NC
I/O
3
A
16
I/O
4
A
14
I/O
5
A
12
I/O
6
A
7
I/O
7
A
6
CE
1
A
5
A
10
A
4
OE
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
STSOP
Top View
(not to scale)
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
7
I/O
6
6
I/O
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
March 29, 2001

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