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CY62128BLL-70ZRXE Datasheet

  • CY62128BLL-70ZRXE

  • 128K x 8 Static RAM

  • 11頁

  • CYPRESS

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CY62128B
MoBL
錚?/div>
128K x 8 Static RAM
Features
鈥?Temperature Ranges
鈥?Commercial: 0擄C to 70擄C
鈥?Industrial: 鈥?0擄C to 85擄C
鈥?Automotive: 鈥?0擄C to 125擄C
鈥?4.5V 鈥?5.5V operation
鈥?CMOS for optimum speed/power
鈥?Low active power
(70 ns, LL version, Commercial, Industrial)
鈥?82.5 mW (max.) (15 mA)
鈥?Low standby power
(70 ns, LL version, Commercial, Industrial)
鈥?110
碌W
(max.) (15
碌A(chǔ))
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
[1]
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
1
),
an active HIGH Chip Enable (CE
2
), an active LOW Output
Enable (OE), and three-state drivers. This device has an
automatic power-down feature that reduces power
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
1
) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O 0
I/O 1
SENSE AMPS
I/O 2
I/O 3
I/O 4
I/O 5
POWER
DOWN
512x 256x 8
ARRAY
CE1
CE2
WE
OE
COLUMN
DECODER
I/O 6
I/O 7
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
Cypress Semiconductor Corporation
Document #: 38-05300 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 14, 2005

CY62128BLL-70ZRXE 產(chǎn)品屬性

  • 156

  • 集成電路 (IC)

  • 存儲器

  • MoBL®

  • RAM

  • SRAM - 異步

  • 1M (128K x 8)

  • 70ns

  • 并聯(lián)

  • 4.5 V ~ 5.5 V

  • -40°C ~ 125°C

  • 32-TFSOP（0.724"，18.40mm 寬）

  • 32-TSOP I

  • 管件

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