Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY54/74FCT543T
SCCS030 - May 1994 - Revised March 2000
8-Bit Latched Registered Transceiver
Functional Description
The FCT543T octal latched transceiver contains two sets of
eight D-type latches with separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) controls for each set to
permit independent control of inputting and outputting in either
direction of data 鏗俹w. For data 鏗俹w from A to B, for example,
the A-to-B enable (CEAB) input must be LOW in order to enter
data from A or to take data from B, as indicated in the truth
table. With CEAB LOW, a LOW signal on the A-to-B latch
enable (LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their output no longer
change with the A inputs. With CEAB and OEAB both LOW,
the three-stage B output buffers are active and re鏗俥ct the data
present at the output of the A latches. Control of data from B
to A is similar, but uses CEAB, LEAB, and OEAB inputs.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Features
鈥?/div>
Function, pinout, and drive compatible with FCT and
F logic
鈥?/div>
FCT-C speed at 5.3 ns max. (Com鈥檒)
FCT-A speed at 6.5 ns max. (Com鈥檒)
鈥?/div>
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?/div>
Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?/div>
Power-off disable feature
鈥?/div>
Matched rise and fall times
鈥?/div>
Fully compatible with TTL input and output logic levels
鈥?/div>
ESD > 2000V
鈥?Sink current
64 mA (Com鈥檒), 48 mA (Mil)
Source current
32 mA (Com鈥檒), 12 mA (Mil)
鈥?/div>
Separation controls for data 鏗俹w in each direction
鈥?/div>
Back to back latches for storage
鈥?/div>
Extended commercial range of
鈭?0藲C
to +85藲C
Functional Block Diagram
Detail A
D Q
LE
A
0
Q D
LE
B
0
Logic Block Diagram
A
0
CEAB
CEBA
LEAB
LEBA
A
1
A
2
A
3
A
4
A
5
A
6
A
7
OEBA
OEAB
CEBA
CEAB
LEBA
LEAB
B
1
B
2
B
3
B
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
OEAB
OEBA
B
1
B
2
B
3
B
4
B
5
B
6
B
7
Detail A x 7
B
4
B
5
B
6
B
7
Pin Configurations
SOIC/QSOP
Top View
LEBA
OEBA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
LEAB
OEAB
Copyright
漏
2000, Texas Instruments Incorporated
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