鈥?/div>
Default on-chip ROM contents for manufacturing/devel-
opment
鈥?2-Kbyte SRAM data buffer for ATA/ATAPI data transfers
鈥?ATA interface supports ATA PIO modes 0鈥?, UDMA modes
0鈥? (multiword DMA not supported). ATA interface
operation mode is automatically selected during device
initialization or manually programmed with I
2
C-compatible
configuration data
鈥?Automatic detection of either Master or Slave ATA/ATAPI
devices
鈥?Mode Page 5 Support鈥搃ncreased support for formatting
removable media devices
鈥?ATA Interrupt support for ATAPI devices鈥搊ffers more robust
ATA support across OS platforms
鈥?System event notification via Vendor-specific ATA
command
鈥?/div>
Input pin for media cartridge detection or ejection request
鈥?/div>
USB bus state indications (Reset, FS/HS mode of oper-
ation, Suspend/Resume, Bus/Self-powered)
鈥?Three General Purpose I/O (GPIO) pins
鈥?Multiple LUNs supported within a single ATAPI device
鈥?ATA translation provides seamless ATA support with
standard MSC drivers
鈥?Additional ATA command support provided by vendor-
specific ATACBs (ATA command blocks utilizing the MSC
Command Block Wrapper)
鈥?Provisions to share ATA bus with other hosts (e.g.
USB/1394 dual device)
鈥?Manufacturing interconnect test support provided with
vendor-specific USB commands:
鈥?/div>
Read/Write access to relevant ASIC pins
鈥?/div>
Manufacturing Interconnect Test Tools
鈥?Utilizes inexpensive 30-Mhz crystal for clock source.
1.1
Functional Block Diagram
VBUS
D+
D-
OSC
nEJECT
SYSIRQ
DRVPWRVLD
DISKRDY
GPIO Pins (3)
nRESET
Control
LOWPWR
CY7C68310
Control Logic
nPWR500
VBUSPWRVLD
VBUSPWRD
ROM
256 Byte
EEPROM
SCL
SDA
EEPROM
Interface
Control
64 Byte
RAM
2kByte FIFO
Bulk
ATA Interface Logic
ATAEN
ATA Control
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document 38-08030 Rev. *H
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 28, 2004
16-bit Data
30MHz
Xtal
USB
USB HS/FS
Control Logic
USB
2.0
Xcvr
next
CY4617 產(chǎn)品屬性
Cypress Semiconductor
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