鈥?/div>
鈥?VHDL or Verilog timing model output for use with
third-party simulators
鈥?Timing simulation provided by Active-HDL鈩?Sim
Release 4.1 from Aldec
鈥?Graphical waveform simulator
鈥?Graphical entry and modification of all waveforms
鈥?Ability to compare waveforms and highlight differ-
ences before and after a design change
鈥?Ability to probe internal nodes
鈥?Display of inputs, outputs, and high-impedance (Z)
signals in different colors
鈥?Automatic clock and pulse creation
鈥?Support for buses
鈥?Unlimited simulation time
鈥?Architecture Explorer and Dynamic Timing Simulator
for PSI and Delta39K devices:
鈥?Graphical representation of exactly how your design
will be implemented on your specific target device
鈥?Zoom from the device level down to the macrocell
level
鈥?Determine the timing for any path and view that path
on a graphical representation of the chip
Static Timing Report for all devices
Source-Level Behavioral Simulation and Debugger
from Aldec
Testbench Generation
C3ISR Programming Cable
Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin PQFP
device
On-line documentation and help
Functional Description
Warp
Enterprise鈩?is an integration of the
Warp
Profes-
sional鈩?CPLD Development package with additional sophis-
ticated EDA software features from Aldec. In addition to
accepting IEEE 1076/1164 VHDL text and graphical finite state
machines for design entry,
Warp
Enterprise VHDL provides a
graphical HDL block diagram editor with a library of graphical
HDL blocks pre-optimized for Cypress devices. Plus, it
provides a utility to convert HDL text into graphical HDL blocks.
Warp
Enterprise synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel
廬
hex file for the desired
PLD or CPLD (see
Figure 1).
For simulation,
Warp
Enterprise
provides a timing simulator, a source-level behavioral
simulator, as well as VHDL and Verilog timing models for use
with third party simulators.
Warp
Enterprise also provides the
designer with important productivity tools such as a testbench
generation wizard and the Architecture Explorer graphical
analysis tool.
Cypress Semiconductor Corporation
Document #: 38-03050 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised August 18, 2003
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