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CY3128
Warp
Professional鈩?CPLD Software
Features
鈥?VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
high-level language compilers with the following fea-
tures:
鈥?Designs are portable across multiple devices
and/or EDA environments
鈥?Facilitates the use of industry-standard simulation
and synthesis tools for board- and system-level
design
鈥?Support for functions and libraries facilitating
modular design methodology
鈥?IEEE Standard 1076 and 1164 VHDL synthesis
supports:
鈥?Enumerated types
鈥?Operator overloading
鈥?For... Generate statements
鈥?Integers
鈥?IEEE Standard 1364 Verilog synthesis supports:
鈥?Reduction and conditional operators
鈥?Blocking and non-blocking procedural assignments
鈥?While loops
鈥?Integers
鈥?Several design entry methods support high-level and
low-level design descriptions:
鈥?Graphical HDL Block Diagram editor and a library of
blocks from Aldec
鈥?Aldec Active-HDL鈩?FSM graphical Finite State
Machine editor
鈥?Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
鈥?Boolean
鈥?Structural Verilog and VHDL
鈥?Designs can include multiple entry methods (but
only one HDL) in a single design.
鈥?Language Assistant library of VHDL and Verilog tem-
plates
鈥?Flow Manager Interface to keep track of complex
projects
鈥?UltraGen鈩?Synthesis and Fitting Technology:
鈥?Infers 鈥渕odules鈥?such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device.
鈥?User-selectable speed and/or area optimization on a
block-by-block basis
鈥?Perfectly integrated synthesis and fitting
鈥?Automatic selection of optimal flip-flop type
(D type/T type)
鈥?Automatic pin assignment
鈥?Support for all Cypress Programmable Logic Devices
鈥?PSI鈩?(Programmable Serial Interface鈩?
鈥?Delta39K鈩?CPLDs
鈥?Quantum38K鈩?CPLDs
鈥?Ultra37000鈩?CPLDs
鈥?F
LASH
370i鈩?CPLDs
鈥?MAX340鈩?CPLDs
鈥?Industry standard PLDs (16V8, 20V8, 22V10)
鈥?VHDL and Verilog timing model output for use with
third-party simulators
鈥?Active-HDL鈩?Sim Release 4.1 timing simulation from
Aldec
鈥?Graphical waveform simulator
鈥?Graphical entry and modification of stimulus wave-
forms
鈥?Ability to compare waveforms and highlight differ-
ences before and after a design change
鈥?Ability to probe internal nodes
鈥?Display of inputs, outputs, and high impedance (Z)
signals in different colors
鈥?Automatic clock and pulse creation
鈥?Support for buses
鈥?Up to 5 ms simulation time
鈥?Architecture Explorer analysis tool and Dynamic Tim-
ing Analysis for PSI, Delta39K and Quantum38K devic-
es:
鈥?Graphical representation of exactly how your design
will be implemented on your specific target device
鈥?Zoom from the device level down to the macrocell
level
鈥?Determine the timing for any path and view that path
on a graphical representation of the chip
鈥?Static Timing Report for all devices
鈥?UltraISR Programming Cable
鈥?Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin PQFP
device
[1]
鈥?On-line documentation and help
Functional Description
Warp
Professional鈩?is an integration of the
Warp
廬
CPLD De-
velopment package with additional sophisticated EDA soft-
ware features from Aldec. In addition to accepting IEEE
1076/1164 VHDL text, IEEE 1364 Verilog text and graphical
finite state machines for design entry,
Warp
Professional pro-
vides a graphical HDL block diagram editor with a library of
graphical HDL blocks pre-optimized for Cypress devices. It
synthesizes and optimizes the entered design, and outputs a
JEDEC or Intel hex file for the desired PLD or CPLD (see
Fig-
ure 1).
For simulation,
Warp
Professional provides a timing
simulator, as well as VHDL timing models for use with third
party simulators.
Warp
Professional also provides the design-
er with important productivity tools like the Architecture Explor-
er graphical analysis tool.
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised January 9, 2002
Note:
1. Cypress reserves the right to substitute prototype boards based on availability.
Cypress Semiconductor Corporation
Document #: 38-03047 Rev. *A
鈥?/div>
3901 North First Street
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