鈥?For... Generate statements
鈥?/div>
Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
鈥?Boolean
鈥?Structural Verilog and VHDL
鈥?Designs can include multiple entry methods (but
only one HDL language) in a single design.
鈥?UltraGen鈩?Synthesis and Fitting Technology:
鈥?Infers 鈥渕odules鈥?such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device.
鈥?User-selectable speed and/or area optimization on a
block-by-block basis
鈥?Perfect communication between synthesis and fit-
ting
鈥?Automatic selection of optimal flip-flop type
(D type/T type)
鈥?Automatic pin assignment
鈥?Supports for the following Cypress Programmable
Logic Devices:
鈥?PSI鈩?(Programmable Serial Interface鈩?
鈥?Delta39K鈩?CPLDs
鈥?Quantum38K鈩?CPLDs
鈥?Ultra37000鈩?CPLDs
鈥?F
LASH
370i鈩?CPLDs
鈥?MAX340鈩?CPLDs
Cypress Semiconductor Corporation
Document #: 38-03046 Rev. *A
鈥?/div>
COMPILATION
UltraGen
TM
Synthesis
and
Fitting
鈥?Industry-standard PLDs (16V8, 20V8, 22V10)
鈥?VHDL and Verilog timing model output for use with
third-party simulators
鈥?Static Timing Report:
鈥?Provides timing information for any path broken
down by the different steps of the path
鈥?Architecture Explorer and Dynamic Timing Analysis for
PSI, Delta39K and Quantum38K devices:
鈥?Graphical representation of exactly how your design
will be implemented on your specific target device
鈥?Zoom from the device level down to the macrocell
level
鈥?Determine the timing for any path and view that path
on a graphical representation of the chip
鈥?Workstation support for Sun Solaris鈩?/div>
鈥?On-line documentation and help
Functional Description
DESIGN
ENTRY
VHDL
Verilog
State Machine
VERFICA TION
Programming
File
Timing
Simulator
VHDL, Verilog
&Third-Party
Simulation Models
Figure 1.
Warp
廬
VHDL Design Flow
Warp
廬
is a state-of-the-art HDL compiler for designing with
Cypress鈥檚 Complex Programmable Logic Devices (CPLDs).
Warp
utilizes a subset of IEEE 1076/1164 VHDL and IEEE
1364 Verilog as its Hardware Description Languages (HDL) for
design entry. Then, it synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel hex file for the desired
PLD or CPLD (see
Figure 1).
Furthermore,
Warp
accepts
VHDL or Verilog produced by the Active-HDL FSM graphical
Finite State Machine editor. For simulation,
Warp
provides a
timing simulator, as well as VHDL and Verilog timing models
for use with third party simulators.
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised January 9, 2002
3901 North First Street
1
2
3
4
5
6
7
8
