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CPLD Development Software for PC
Features
鈥?VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
high-level language compilers with the following
features
鈥?Designs are portable across multiple devices
and/or EDA environments
鈥?Facilitates the use of industry-standard simulation
and synthesis tools for board and system-level
design
鈥?Support for functions and libraries facilitating
modular design methodology
鈥?IEEE Standard 1076 and 1164 VHDL synthesis supports
鈥?Enumerated types
鈥?Operator overloading
鈥?For... Generate statements
鈥?Integers
鈥?IEEE Standard 1364 Verilog synthesis supports
鈥?Reduction and conditional operators
鈥?Blocking and non-blocking procedural assignments
鈥?While loops
鈥?Integers
鈥?Several design entry methods support high-level and
low-level design descriptions
鈥?Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
鈥?Boolean
鈥?Aldec Active-HDL鈩?FSM graphical Finite State
Machine editor
鈥?Structural Verilog and VHDL
鈥?Designs can include multiple entry methods (but
only one HDL language) in a single design
鈥?UltraGen鈩?Synthesis and Fitting Technology
鈥?Infers 鈥渕odules鈥?such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device
鈥?User selectable speed and/or area optimization on a
block-by-block basis
鈥?Perfect communication between synthesis and
fitting
鈥?Automatic selection of optimal flip-flop type
(D type/T type)
鈥?Automatic pin assignment
鈥?Ability to specify timing constraints for all of the
Delta39K and PSI devices
鈥?Supports all Cypress Programmable Logic Devices
鈥?PSI鈩?(Programmable Serial Interface)
鈥?Delta39K鈩?Complex Programmable Logic Devices
(CPLDs)
鈥?Ultra37000鈩?CPLDs
鈥?F
LASH
370i鈩?CPLDs
鈥?MAX340鈩?CPLDs
鈥?Industry standard PLDs (16V8, 20V8, 22V10)
鈥?VHDL and Verilog timing model output for use with
third-party simulators
鈥?Timing simulation provided by Active-HDL鈩?Sim
Release 3.3 from Aldec
鈥?Graphical waveform simulator
鈥?Entry and modification of on-screen waveforms
鈥?Ability to probe internal nodes
鈥?Display of inputs, outputs, and high impedance (Z)
signals in different colors
鈥?Automatic clock and pulse creation
鈥?Support for buses
鈥?Architecture Explorer and Dynamic Timing Analysis for
PSI and Delta39K devices
鈥?Graphical representation of exactly how your design
will be implemented on your specific target device
鈥?Zoom from the device level down to the macrocell
level
鈥?Determine the timing for any path and view that path
on a graphical representation of the chip
鈥?Static Timing Report for all devices
鈥?PC Support (Windows 98鈩? Windows NT鈩?4.0, and
Windows XP鈩?
鈥?On-line documentation and help
Cypress Semiconductor Corporation
Document #: 38-03049 Rev. *C
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3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised August 18, 2002
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