CY2SSTV16857
14-Bit Registered Buffer PC2700-/PC3200-Compliant
Features
鈥?Differential Clock Inputs up to 280 MHz
鈥?Supports LVTTL switching levels on the RESET pin
鈥?Output drivers have controlled edge rates, so no
external resistors are required
鈥?Two KV ESD protection
鈥?Latch-up performance exceeds 100 mA: JESD78, Class II
鈥?Conforms to JEDEC STD(JESD82-3) for buffered DDR
DIMMs
鈥?48-pin TSSOP
When RESET is LOW, the differential input receivers are
disabled, and undriven (floating) data, clock, and REF voltage
inputs are allowed. In addition, when RESET is LOW, all
registers are reset and all outputs force to the LOW state. The
LVCMOS RESET input must always be held at a valid logic
HIGH or LOW level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the LOW
state during power-up.
In the DDR registered DIMM application, RESET is specified
to be completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven LOW quickly, relative to the time to
disable the differential input receivers, thus ensuring no
glitches on the output. However, when coming out of reset, the
register will become active quickly, relative to the time to
enable the differential input receivers. As long as the data
inputs are low, and the clock is stable during the time from the
LOW-to-HIGH transition of RESET till the input receivers are
fully enabled, the design must ensure that the outputs will
remain LOW.
Description
This 14-bit registered buffer is designed specifically for 2.3V to
2.7V V
DD
operation and is characterized for operation from
0擄C to + 85擄C.
All inputs are compatible with the JEDEC Standard for
SSTL_2, except the LVCMOS reset (RESET) input. All outputs
are SSTL_2, Class II-compatible.
The SSTV16857 operates from a differential clock (CLK and
CLK). Data is measured at the crossing of CLK going HIGH,
and CLK going LOW.
Block Diagram
Pin Configuration
Q1
Q2
VSS
VDDQ
Q3
Q4
Q5
VSS
VDDQ
Q6
Q7
VDDQ
VSS
Q8
Q9
VDDQ
VSS
Q10
Q11
Q12
VDDQ
VSS
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
VSS
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
VSS
VREF
RESET
D8
D9
D10
D11
D12
VDD
VSS
D13
D14
RESET
CLK
CLK
VREF
D1
1D
C1
R
Q1
To 13 Other Channels
Cypress Semiconductor Corporation
Document #: 38-07443 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised October 30, 2003
CY2SSTV16857
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