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CY2PP326 Datasheet

  • CY2PP326

  • Clocks and Buffers

  • 10頁

  • ETC

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PRELIMINARY
FastEdge鈩?Series
CY2PP326
2 x 2 Clock and Data Switch Buffer
Features
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Six LVPECL differential outputs grouped in two banks
Two LVPECL differential inputs
Hot-swappable/-insertable
50-ps output-to-output skew
< 500-ps device-to-device skew (typical)
Less than < 3-ps intrinsic jitter
400-ps propagation delay (typical)
Operation up to 1.20 GHz
LVPECL mode supply range: V
CC
= 2.375V to 3.465V
Industrial temperature range: 鈥?0擄C to 85擄C
32-pin 1.4-mm TQFP package
Temperature compensation like 100K ECL
Description
The CY2PP326 is a low-skew, low propagation delay 2 x 2
differential clock, data switch, and fanout buffer targeted to
meet the requirements of high-performance clock and data
distribution applications. The device is implemented on SiGe
technology and has a fully differential internal architecture that
is optimized to achieve low-signal skews at operating
frequencies of up to 1.20 GHz.
The device features two differential input paths which are mul-
tiplexed internally to six outputs grouped in two banks. The
muxes are controlled by SEL(0:1) control inputs. The
CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and
as a clock/data repeater or multiplexer.
Since the CY2PP326 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems and for switching data signals
between different channels. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP326 delivers consistent, guaranteed
performance over differing platforms.
Block Diagram
Pin Configuration
QA0#
QA1#
VCC
VCC
QA0
QA1
CLK0
CLK0#
0
QA1
QA1#
1
QA2
QA2#
VCC
GND
SEL1
CLK1
CLK1#
OEB#
GND
VCC
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
QA2
QA0
QA0#
QA2#
VCC
Bank A
VCC
GND
OEA#
CLK0
CLK0#
SEL0
GND
VCC
VCC
Bank B
CLK1
CLK1#
0
1
QB0
QB0#
QB1
QB1#
QB2
QB2#
CY2PP326
21
20
19
18
17
SEL0
SEL1
9
QB0#
10 11 12 13 14 15 16
VCC
QB1#
VCC
QB0
QB1
QB2#
QB2
OEA#
OEB#
Sync
Cypress Semiconductor Corporation
Document #: 38-07506 Rev. *B
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3901 North First Street
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San Jose
,
CA 95134
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408-943-2600
Revised September 8, 2003

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