鈥?/div>
Two sets of ten ECL/PECL differential outputs
Two ECL-/PECL-differential inputs
Hot-swappable/-insertable
50-ps output-to-output skew
< 500-ps device-to-device skew
Less than 10-ps intrinsic jitter
500-ps propagation delay (typical)
Operation from DC to 1.5 GHz
PECL supply range: V
CC
= 2.375V to 3.465V
with V
EE
= 0V
ECL mode supply range: V
EE
= 鈥?.375V to 鈥?.465V
with V
CC
= 0V
Industrial temperature range: 鈥?0
擄
C to 85
擄
C
52-pin 1.4-mm TQFP package
Temperature compensation like 100K ECL
Description
The CY2PP3220 is a low-skew, low propagation delay, dual
1-to-10 differential fanout buffer targeted to meet the require-
ments of high-performance clock and data distribution applica-
tions. The device is implemented on SiGe technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to
1.5 GHz.
The device features two differential input paths which are
differential internally. The CY2PP3220 may function not only
as a differential clock buffer but also as a signal level translator
and fanout ECL/PECL single-ended or differential signals to
twenty ECL/PECL differential loads. An external bias pin, VBB,
is provided for distributing a single-ended signal. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to V
CC
via a
0.01-碌F capacitor. Traditionally, in ECL, it is used to provide
the reference level to a receiving single ended input that might
have a different self bias point.
Since the CY2PP3220 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high-frequency,
high-precision clocks across backplanes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3220 delivers consistent, guaranteed
performance over differing platforms.
Block Diagram
QA0#
Pin Configuration
VCCO
QA1#
QA2#
QA3#
QA4#
QA5#
QA0
QA1
QA2
QA3
QA4
CLKA
CLKA#
VCC
QA0
QA0#
VCCO
VEE
VEE
QA9
QA9#
QB0
QB0#
VCC
VEE
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
QB9#
QB9
QB8#
QB8
52 51 50 49 48 47 46 45 44 43 42 41 40
39
1
38
2
37
3
4
5
6
7
8
9
10
11
12
36
35
34
QA5
QA6
QA6#
QA7
QA7#
QA8
QA8#
QA9
QA9#
QB0
QB0#
QB1
QB1#
VCCO
CLKB
CLKB#
VCC
CY2PP3220
33
32
31
30
29
28
VEE
VEE
QB9
QB9#
VBB
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
VCCO
QB7#
QB7
QB6#
QB6
QB5#
QB5
QB4#
QB4
QB3#
QB3
QB2#
Cypress Semiconductor Corporation
Document #: 38-07513 Rev.*A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised April 15, 2003
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