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CY2PP318 Datasheet

  • CY2PP318

  • Clocks and Buffers

  • 12頁

  • ETC

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PRELIMINARY
FastEdge鈩?Series
CY2PP318
1 of 2:8 Differential Fanout Buffer
Features
鈥?Eight ECL/PECL differential outputs
鈥?Two ECL/PECL differential inputs
鈥?Hot-swappable/-insertable
鈥?50-ps output-to-output skew
鈥?< 500-ps device-to-device skew
鈥?Less than 10 ps intrinsic jitter
鈥?500-ps propagation delay (typical)
鈥?Operation up to 1.5 GHz
鈥?PECL mode supply range: V
CC
= 2.375V to 3.465V with
V
EE
= 0V
鈥?ECL mode supply range: V
E E
= 鈥?.375V to 鈥?.465V with
V
CC
= 0V
鈥?Industrial temperature range: 鈥?0擄C to 85擄C
鈥?28-pin PLCC package
鈥?Temperature compensation as 100K ECL
Description
The CY2PP318 is a low-skew, low propagation delay 1-to-8
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2PP318 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on
ECL/PECL signal to eight ECL/PECL differential loads. An ex-
ternal bias pin, VBB, is provided for this purpose. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to ground via a
0.01-碌F capacitor.
Since the CY2PP318 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP318 delivers consistent, guaranteed
performance over different platforms.
Block Diagram
Q0
Q0#
Pin Configuration
Q1
Q1#
VCCO
CLKA
CLKA#
Q2
Q2#
Q3
VCCOVEE
Q3#
Q4
Q4#
VEE
CLK_SEL
Q5
Q5#
CLK_SEL
CLKA#
VCCO
CLKA
CLKB
4
VBB
3
VEE
28
27
26
2
1
CLKB#
NC
Q 7#
VCCO
Q7
Q 6#
Q6
Q0
Q 0#
Q1
VCCO
Q 1#
Q2
Q 2#
25 24 23 22 21 20 19
5
6
7
8
9
10 11
TOP VIEW
CY2PP318
CLKB
CLKB#
13
Q5
14
15
12
Q5#
16
Q4
17
18
Q4#
VCCO
Q3#
Q3
VEE
Q6
Q6#
VBB
Q7
Q7#
Cypress Semiconductor Corporation
Document #: 38-07501 Rev.*B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 8, 2004

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