PRELIMINARY
FastEdge鈩?Series
CY2PP3115
1:15 Differential Fanout Buffer
Features
鈥?Fifteen ECL/PECL differential outputs grouped in four
banks
鈥?Two ECL/PECLdifferential inputs
鈥?Hot-swappable/-insertable
鈥?50-ps output-to-output skew
鈥?< 200-ps device-to-device skew
鈥?Less than 2-pS intrinsic jitter
鈥?< 500-ps propagation delay (typical)
鈥?Operation up to 1.5 GHz
鈥?PECL mode supply range: V
CC
= 2.375V to 3.465V with
V
EE
= 0V
鈥?ECL mode supply range: V
EE
= 鈥?.375V to 鈥?.465V with
V
CC
= 0V
鈥?Industrial temperature range: 鈥?0
擄
C to 85
擄
C
鈥?52-pin 1.4mm TQFP package
鈥?Temperature compensation like 100K ECL
Description
The CY2PP3115 is a low-skew, low propagation delay 1-to-15
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low-signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths which are
multiplexed internally. This mux is controlled by the CLK_SEL
pin. The CY2PP3115 may function not only as a differential
clock buffer but also as a signal level translator and fanout on
ECL/PECL single-ended signal to 15 ECL/PECL differential
loads. An external bias pin, VBB, is provided for this purpose.
In such an application, the VBB pin should be connected to
either one of the CLKA# or CLKB# inputs and bypassed to V
CC
via a 0.01-碌F capacitor.
Since the CY2PP3115 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3115 delivers consistent, guaranteed
performance over differing platforms.
Block Diagram
FSELA
VEE
VCC
1
CLK0
CLK0#
0
VCC VEE
1
CLK1
CLK1#
VEE
CLK_SEL
VEE
1
FSELB
FSELC
QC2
QC3
0
/2
1
/1
0
QB1
QB2
0
QAO
QA1
Pin Configuration
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
14
15
16
17
18
19
20
21
22
23
24
25
26
27
QBO
VCC
QA0
QA0#
QA1
QA1#
VCC
QB0
QB0#
QB1
QB1#
QB2
QB2#
VCC
VCC
MR
FSELA
FSELB
CLK0
QC0
QC1
1
2
3
4
5
6
7
8
9
10
11
12
13
VCC
QC0
QC0#
QC1
QC1#
QC2
QC2#
QC3
QC3#
VCC
NC
NC
VCC
CLK0#
CLK_SEL
CLK1
CLK1#
VBB
FSELC
FSELD
VEE
CY2PP3115
VEE
MR
VEE
0
QD0
QD1
QD2
QD3
QD4
1
FSELD
VEE
QD5
VBB
Cypress Semiconductor Corporation
Document #: 38-07502 Rev.*A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 18, 2003
VCC
QD5#
QD5
QD4#
QD4
QD3#
QD3
QD2#
QD2
QD1#
QD1
QD0#
QD0
1
2
3
4
5
6
7
8
9
10
11
12
