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CY2LL843 Datasheet

  • CY2LL843

  • Clocks and Buffers

  • 13頁(yè)

  • ETC

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ComLink鈩?Series
CY2LL843
High-drive Two-Channel LVDS Repeater/Mux
Features
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ANSI TIA/EIA-644-1995-compliant
Designed for data rates to > 700 Mbs = (350 MHz)
Single 2 脳 2 with high-drive output drivers
Low -voltage differential signaling with output voltages
of
鹵
350 mV into 50-ohm load version (Bus LVDS)
Single 3.3V supply
Accepts
鹵
350-mV differential inputs
Output Drivers are high-impedance when disabled or
when V
DD
鈮?.5V
16-pin SOIC/TSSOP packages
Industrial version available
achieve signaling rates of 700Mbs. The receiver outputs can
be switched to either or both drivers through the multiplexer
control signals S0/S1. This provides flexibility in application for
either a splitter or router configuration with a single device.
The Cypress CY2LL843 are configured as a single
two-channel repeater/Mux.
The LVDS standard provides a minimum differential output
voltage of 247 mV into a 50-ohm load and receipt of as little as
100 mV signals with up to 1V of DC offset between transmitter
and receiver. The Cypress CY2LL843 doubles the output drive
current to achieve BusLVDS signaling levels with a faster
rise/fall times into 50-ohm load.
A doubly terminated BusLVDS line enables multipoint config-
urations.
Designed for both point to point based-band multi-point data
transmission over controlled impedance lines.
Description
The Cypress CY2LL843 are differential line drivers and
receivers that utilize Low Voltage Signaling or LVDS, to
Block Diagram
Pin Configuration
VDD
1DE
1A
1B
2A
2B
1Y
1Z
2Y
2Z
1B
GND
1A
2DE
CY2LL843
S0
1DE
S1
2A
2B
GND
S0
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VDD
1Y
1Z
2DE
2Z
2Y
GND
16 pin SOIC/TSSOP
Cypress Semiconductor Corporation
Document #: 38-07066 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised December 14, 2002

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