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CY2LL842 Datasheet

  • CY2LL842

  • Clocks and Buffers

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  • ETC

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ComLink鈩?Series
CY2LL842
Two-channel LVDS Repeater/Mux
Features
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ANSI TIA/EIA-644-1995-compliant
Does not exceed Belcore 802.3 standards
Operation at => 350 MHz鈥?00 Mbps
Single 2 脳 2
Low-voltage differential signaling (LVDS) with output
voltages of
鹵
350 mV into 100-ohm load version (Std)
Single 3.3V supply
Accepts
鹵
350 mV differential inputs
Output drivers are high-impedance when disabled or
when V
DD
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1.5V
16-pin SOIC/TSSOP packages
Industrial version available
Description
The CYPRESS CY2LL842 are differential line drivers and
receivers that utilize LVDS to achieve signaling rates of 650
Mbs. The receiver outputs can be switched to either or both
drivers thru the multiplexer control signals S0/S1. This
provides flexibility in application for either a splitter or router
configuration with a single device.
The CYPRESS CY2LL842 is configured as a single
two-channel repeater/Mux.
The LVDS standard provides a minimum differential output
voltage of 247 mV into a 100-ohm load and receipt of as little
as 100-mV signals with up to 1V of DC offset between trans-
mitter and receiver.
A doubly terminated bus LVDS line enables multipoint config-
urations.
Designed for both point to point based-band multi-point data
transmission over controlled impedance lines.
Block Diagram
Pin Configuration
1B
VDD
1DE
1A
S0
1A
1B
2A
2B
1Y
1Z
2Y
2Z
1DE
S1
2A
2B
GND
GND
2DE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VDD
1Y
1Z
2DE
2Z
2Y
GND
S0 S1
16 pin SOIC/TSSOP
Cypress Semiconductor Corporation
Document #: 38-07063 Rev. *A
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3901 North First Street
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San Jose
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CY2LL842
CA 95134 鈥?408-943-2600
Revised December 15, 2002

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