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CY2LL8422 Datasheet

  • CY2LL8422

  • Clocks and Buffers

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8422
COMLINK鈩?SERIES
CY2LL8422
High Drive Dual 2-Channel LVDS Repeater/Mux
Features
鈥?ANSI TIA/EIA-644-1995 Compliant
鈥?Designed for Data rates to 650 MBps = (325 MHz)
鈥?Dual 2x2
鈥?/div>
Low Voltage Differential Signaling with output volt-
ages of
鹵350
mV into 100-ohm load version (Std)
鈥?Single 3.3V supply
鈥?/div>
Accepts
鹵35
mV differential inputs
鈥?Output drivers are high impedance when disabled or
when V
DD
<1.5V
鈥?28-pin SSOP/TSSOP packages
鈥?Industrial version available
Description
The Cypress CY2LL8422 are differential line drivers and re-
ceivers that utilize Low Voltage Signaling or LVDS, to achieve
signaling rates of 650 MBps. The receiver outputs can be
switched to either or both drivers through the multiplexer con-
trol signals S2/S3. This provides flexibility in application for
either a splitter or router configuration with a single device.
The Cypress CY2LL8422 are configured as dual 2-channel
repeaters/Muxes.
The LVDS standard provides a minimum differential output
voltage of 247 mV into a 100-ohm load and receipt of as little
as 100 mV signals with up to 1V of DC offset between trans-
mitter and receiver.
A doubly terminated Bus LVDS line enables multipoint con-
figurations.
Designed for both point-to-point based-band multipoint data
transmission over controlled impedance lines.
Block Diagram
Pin Configuration
1DE
4
1A
1B
2A
2B
2
1
6
7
27
26
23
24
25
3
5
2DE
1Y
1Z
2Y
2Z
S0S1
3DE
11
3A
3B
4A
4B
8
9
13
14
20
19
17
16
18
10
12
4DE
3Y
3Z
4Y
4Z
1B
1A
S0
1DE
S1
2A
2B
3A
3B
S2
3DE
S3
4A
4B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY2LL8422
VDD
1Y
1Z
2DE
2Z
2Y
GND
VDD
3Y
3Z
4DE
4Y
4Z
GND
28pin TSSOP/SSOP
S2 S3
Cypress Semiconductor Corporation
Document #: 38-07411 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?408-943-2600
Revised July 3, 2002

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