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CY2DP814ZCT Datasheet

  • CY2DP814ZCT

  • 1:4 Clock Fanout Buffer

  • 122.73KB

  • 9頁

  • CYPRESS

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ComLink鈩?Series
CY2DP814
1:4 Clock Fanout Buffer
Features
Low voltage operation
V
DD
= 3.3V
1:4 fanout
Single-input configurable for LVDS, LVPECL, or LVTTL
Four differential pairs of LVPECL outputs
Drives 50-ohm load
Low input capacitance
Low output skew
Low propagation delay
鈥?Typical (tpd < 4 ns)
鈥?Industrial versions available
鈥?Available packages include TSSOP, SOIC
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Description
The Cypress CY2 series of network circuits are produced
using advanced 0.35-micron CMOS technology, achieving the
industry鈥檚 fastest logic.
The Cypress CY2DP814 fanout buffer features a single LVDS-
or a single LVPECL-compatible input and four LVPECL output
pairs.
Designed for data communications clock management appli-
cations, the fanout from a single input reduces loading on the
input clock.
The CY2DP814 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVDS-based clock signals. The Cypress CY2DP814 has
configurable input between logic families. The input can be
selectable for an LVPECL/LVTTL or LVDS signal, while the
output drivers support LVPECL capable of driving 50-ohm
lines.
Block Diagram
Pin Configuration
EN1 1
EN2 8
16 Q1A
15 Q1B
EN1
CONFIG
VDD
VDD
GND
IN+
IN-
IN+ 6
IN- 7
LVDS /
LVPECL /
LVTTL
CONFIG 2
14 Q2A
13 Q2B
12 Q3A
11 Q3B
EN2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
10 Q4A
9 Q4B
16 pin TSSOP / SOIC
OUTPUT
LVPECL
Cypress Semiconductor Corporation
Document #: 38-07060 Rev. *B
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised December 15, 2002
CY2DP814

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